%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

llvm-svn: 47534

llvm-svn: 47533

for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532

llvm-svn: 47531

llvm-svn: 47529

llvm-svn: 47527

If remating a machine instr with virtual register operand, make sure the vr is avaliable at all uses regardless of whether it would be folded.

llvm-svn: 47526

llvm-svn: 47525

llvm-svn: 47524

invalid command-line options.

llvm-svn: 47523

No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.

llvm-svn: 47522

llvm-svn: 47521

Recognize loads of arguments as re-materializable first. Therefore if isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction.

llvm-svn: 47520

llvm-svn: 47519

llvm-svn: 47518

llvm-svn: 47517

llvm-svn: 47516

llvm-svn: 47514

llvm-svn: 47513

llvm-svn: 47511

llvm-svn: 47510

llvm-svn: 47509

To support multiple return values, now ret instruction supports multiple operands instead of one aggregate operand.

llvm-svn: 47508

llvm-svn: 47507

stuff into ParamAttrsList.h.  Per feedback from
ParamAttrs changes.

llvm-svn: 47504

llvm-svn: 47503

llvm-svn: 47502

llvm-svn: 47501

llvm-svn: 47500

Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.

llvm-svn: 47499

llvm-svn: 47496

llvm-svn: 47495

llvm-svn: 47494

llvm-svn: 47493

llvm-svn: 47492

llvm-svn: 47488

llvm-svn: 47485

the way through.  It is now used for codegen.

llvm-svn: 47484

llvm-svn: 47483

llvm-svn: 47482