llvm-svn: 139485

Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.

llvm-svn: 139479

r139454 activates an assert in a case where we were doing the right thing anyway.  Make that explicit, and un-XFAIL the testcase.

llvm-svn: 139458

lib/ExecutionEngine/MCJIT/MCJIT.cpp from:

  assert("error");

to:

  assert(0 && "error");

llvm-svn: 139456

  assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

llvm-svn: 139432

llvm-svn: 139431

llvm-svn: 139429

llvm-svn: 139422

llvm-svn: 139421

llvm-svn: 139420

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

llvm-svn: 139412

llvm-svn: 139405

Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

llvm-svn: 139400

llvm-svn: 139399

llvm-svn: 139389

llvm-svn: 139383

llvm-svn: 139381

Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.

llvm-svn: 139353

removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344

llvm-svn: 139339

llvm-svn: 139329

llvm-svn: 139328

llvm-svn: 139324

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320

single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

llvm-svn: 139311

in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305

Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304

llvm-svn: 139285

More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272

Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270

Remove the "common" set of instructions shared between ARM and Thumb2 modes.  This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.

llvm-svn: 139268

llvm-svn: 139267

llvm-svn: 139264

llvm-svn: 139263

llvm-svn: 139258

llvm-svn: 139256