llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

llvm-svn: 139459

  assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433

llvm-svn: 139432

llvm-svn: 139422

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type.  Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs.  Fixes PR10897.

llvm-svn: 139407

llvm-svn: 139405

Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

llvm-svn: 139400

llvm-svn: 139399

llvm-svn: 139397

llvm-svn: 139396

llvm-svn: 139395

llvm-svn: 139393

llvm-svn: 139392

llvm-svn: 139391

llvm-svn: 139390

llvm-svn: 139389

llvm-svn: 139386

llvm-svn: 139385

llvm-svn: 139383

llvm-svn: 139381

llvm-svn: 139371

any given function.  As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.

llvm-svn: 139360

llvm-svn: 139356

removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344

Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.

llvm-svn: 139330

llvm-svn: 139328

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320

llvm-svn: 139318

without a base symbol that must not have a relocation entry.

llvm-svn: 139316

llvm-svn: 139309

in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305

Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304

llvm-svn: 139292

llvm-svn: 139288