llvm-svn: 54128

Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions.

llvm-svn: 53844

llvm-svn: 53784

replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728

has exactly one MachineMemOperand, and change some X86 lowering code to
make use of it.

llvm-svn: 53498

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

llvm-svn: 53177

- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097

llvm-svn: 53060

Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction.

llvm-svn: 52670

llvm-svn: 52308

and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044

load-folding table entries for PMULDQ and PMULLD.

llvm-svn: 51489

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091

"is{Trivially,Really}ReMaterializable" methods.

llvm-svn: 51001

llvm-svn: 50578

Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address.

llvm-svn: 50574

llvm-svn: 50007

llvm-svn: 49830

Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented

llvm-svn: 49809

review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348

ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now.

llvm-svn: 49059

llvm-svn: 49054

llvm-svn: 49037

llvm-svn: 49002

llvm-svn: 48995

llvm-svn: 48977

llvm-svn: 48922

llvm-svn: 48911

llvm-svn: 48856

llvm-svn: 48855

llvm-svn: 48854

other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777

ST(0)/ST(1).

llvm-svn: 48634

Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.

llvm-svn: 48412

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

llvm-svn: 48241

llvm-svn: 48240