It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280

Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944

llvm-svn: 91571

bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496

llvm-svn: 91434

llvm-svn: 90246

llvm-svn: 89478

llvm-svn: 89328

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

llvm-svn: 86019

llvm-svn: 85980

between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874

llvm-svn: 85824

llvm-svn: 85698

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

Patch by Sylvere Teissier.

llvm-svn: 83135

llvm-svn: 81306

llvm-svn: 80956

llvm-svn: 80615

llvm-svn: 80350

llvm-svn: 80322

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

llvm-svn: 79535

llvm-svn: 79436

llvm-svn: 79318

llvm-svn: 79014

llvm-svn: 78970

llvm-svn: 78908

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78790

llvm-svn: 78778

llvm-svn: 78745

llvm-svn: 78717

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78610