llvm-svn: 105168

The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

llvm-svn: 105164

llvm-svn: 105109

llvm-svn: 105108

llvm-svn: 105107

llvm-svn: 105106

llvm-svn: 105105

shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.

llvm-svn: 105101

llvm-svn: 105100

llvm-svn: 105098

llvm-svn: 105096

llvm-svn: 105095

Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.

llvm-svn: 105092

llvm-svn: 105066

llvm-svn: 105065

Also verify that all subregister indices compose unambiguously.

llvm-svn: 105064

were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063

llvm-svn: 105061

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 105059

llvm-svn: 105014

llvm-svn: 105012

llvm-svn: 105009

as is done with most other cast opcode predicates.

llvm-svn: 105008

llvm-svn: 105006

llvm-svn: 105005

llvm-svn: 105001

getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994

llvm-svn: 104993

llvm-svn: 104992

implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

llvm-svn: 104985

llvm-svn: 104980

llvm-svn: 104974

llvm-svn: 104970

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

llvm-svn: 104963

llvm-svn: 104962

llvm-svn: 104961

llvm-svn: 104959

llvm-svn: 104958