[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.

llvm-svn: 192160

They haven't been used for a long time. Patch by MathOnNapkins.

llvm-svn: 192099

llvm-svn: 192056

This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.

llvm-svn: 192054

addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053

llvm-svn: 192023

llvm-svn: 192015

llvm-svn: 192006

llvm-svn: 191432

llvm-svn: 191180

[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.

llvm-svn: 191168

[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.

llvm-svn: 191167

[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.

llvm-svn: 191166

Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.

Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.

This should fix PR15840.

llvm-svn: 191165

llvm-svn: 191164

llvm-svn: 191160

llvm-svn: 191158

llvm-svn: 191154

In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.

This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.  

llvm-svn: 190033

  This assertion is triggered because an integer constant is created with wrong
  type.

llvm-svn: 189948

llvm-svn: 189780

llvm-svn: 189768

llvm-svn: 189198

llvm-svn: 189195

llvm-svn: 189085

This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.

This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.

llvm-svn: 189084

[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.

llvm-svn: 188738

llvm-svn: 188141

Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.

Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

llvm-svn: 187780

register i7 as a live-in if current function's return address is taken.

This revision fixes PR16269.

llvm-svn: 187433

llvm-svn: 187402

llvm-svn: 186274

and loadRegFromStackSlot.

llvm-svn: 184935

llvm-svn: 184642

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

llvm-svn: 184360

Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067

llvm-svn: 183613

llvm-svn: 183589

llvm-svn: 183587

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183565