llvm-svn: 132479

rdar://problem/6373334

llvm-svn: 132458

No functional change.

llvm-svn: 132455

llvm-svn: 132451

llvm-svn: 132448

llvm-svn: 132444

llvm-svn: 132424

llvm-svn: 132419

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398

patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388

llvm-svn: 132355

llvm-svn: 132341

llvm-svn: 132340

llvm-svn: 132336

must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324

nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

directives.

Fixes PR9826.

llvm-svn: 132317

llvm-svn: 132315

same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314

subregisters of the 64 bit ones.

llvm-svn: 132313

and for now the generic dwarf emission will automatically use the superregister
numbers.

llvm-svn: 132312

This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.

llvm-svn: 132295

llvm-svn: 132293

This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

llvm-svn: 132291

llvm-svn: 132278

llvm-svn: 132276

and should probably be encoded as

DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33

llvm-svn: 132274

-verify-machineinstrs failures on several tests.

llvm-svn: 132268

to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

llvm-svn: 132248

llvm-svn: 132246

in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.

 

llvm-svn: 132243

register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242

Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240

llvm-svn: 132238

and add some basic tests for them.

llvm-svn: 132235

mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

llvm-svn: 132233

llvm-svn: 132230

was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

llvm-svn: 132225