llvm-svn: 132131

llvm-svn: 132128

llvm-svn: 132127

llvm-svn: 132108

llvm-svn: 132107

rdar://problem/6920088

llvm-svn: 132105

Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.

The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099

llvm-svn: 132098

llvm-svn: 132086

llvm-svn: 132083

Part of rdar://9119939

llvm-svn: 132081

been defined in MipsInstrFPU.td.

llvm-svn: 132076

llvm-svn: 132074

llvm-svn: 132073

llvm-svn: 132070

return 0 if there are no function calls made. 

llvm-svn: 132065

llvm-svn: 132063

llvm-svn: 132062

MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.

llvm-svn: 132057

llvm-svn: 132044

llvm-svn: 132043

fixes <rdar://problem/9495913>

llvm-svn: 132042

target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

llvm-svn: 132041

llvm-svn: 132040

reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039

LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

llvm-svn: 132033

llvm-svn: 132030

Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026

Part of rdar://9119939

llvm-svn: 132024

Part of rdar://9119939

llvm-svn: 132023

do.

Part of rdar://9119939.

llvm-svn: 132015

Fixes part of rdar://9444657

llvm-svn: 132011

offsets that are larger than 0x10000.

llvm-svn: 132003

deficiencies exist:

- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.

llvm-svn: 131986

llvm-svn: 131974

scheme uses internally. Implement it for x86 (the only architecture that LLVM
supports for which this matters right now).

llvm-svn: 131969

  non-zero.
- Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension
  when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero.

rdar://9490949

llvm-svn: 131948

variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.

llvm-svn: 131942

llvm-svn: 131928

llvm-svn: 131927