- Nov 16, 2007
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Anton Korobeynikov authored
Codegen bits and llvm-gcc support will follow. llvm-svn: 44182
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- Nov 15, 2007
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Nate Begeman authored
llvm-svn: 44181
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Duncan Sands authored
llvm-svn: 44167
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Evan Cheng authored
llvm-svn: 44166
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Bill Wendling authored
llvm-svn: 44154
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Bill Wendling authored
llvm-svn: 44153
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- Nov 14, 2007
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Anton Korobeynikov authored
to all targets uses GOT-relative offsets for PIC (Alpha?) llvm-svn: 44108
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Evan Cheng authored
MachineOperand auxInfo. Previous clunky implementation uses an external map to track sub-register uses. That works because register allocator uses a new virtual register for each spilled use. With interval splitting (coming soon), we may have multiple uses of the same register some of which are of using different sub-registers from others. It's too fragile to constantly update the information. llvm-svn: 44104
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- Nov 13, 2007
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Owen Anderson authored
interference. llvm-svn: 44064
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Owen Anderson authored
llvm-svn: 44063
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Dale Johannesen authored
to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
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Bill Wendling authored
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... llvm-svn: 44037
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- Nov 12, 2007
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Owen Anderson authored
llvm-svn: 44019
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Evan Cheng authored
llvm-svn: 44010
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Owen Anderson authored
to be a pass of its own. Instead, move it out into a helper method. llvm-svn: 44002
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- Nov 09, 2007
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Hartmut Kaiser authored
llvm-svn: 43960
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Duncan Sands authored
llvm-svn: 43944
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Duncan Sands authored
apints on big-endian machines if the bitwidth is not a multiple of 8. Introduce a new helper, MVT::getStoreSizeInBits, and use it. llvm-svn: 43934
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Duncan Sands authored
llvm-svn: 43933
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Evan Cheng authored
Then: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry imull $4, %ecx, %ecx leal LJTI1_0-"L1$pb"(%eax), %edx addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx jmpl *%edx .align 2 .set L1_0_set_3,LBB1_3-LJTI1_0 .set L1_0_set_2,LBB1_2-LJTI1_0 .set L1_0_set_5,LBB1_5-LJTI1_0 .set L1_0_set_4,LBB1_4-LJTI1_0 LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 Now: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax jmpl *%eax .align 2 .set L1_0_set_3,LBB1_3-"L1$pb" .set L1_0_set_2,LBB1_2-"L1$pb" .set L1_0_set_5,LBB1_5-"L1$pb" .set L1_0_set_4,LBB1_4-"L1$pb" LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 llvm-svn: 43924
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Evan Cheng authored
llvm-svn: 43923
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Evan Cheng authored
llvm-svn: 43922
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- Nov 08, 2007
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Owen Anderson authored
llvm-svn: 43911
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Owen Anderson authored
llvm-svn: 43910
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Evan Cheng authored
If both parts of smul_lohi, etc. are used, don't simplify. If only one part is used, try simplify it. llvm-svn: 43888
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Owen Anderson authored
Add the majority of machine-level critical edge breaking pass. Most of this was written by Fernando, cleanup and updating to TOT by me. This still needs a bit of work, particularly to handle jump tables properly. llvm-svn: 43885
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Owen Anderson authored
llvm-svn: 43869
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Owen Anderson authored
llvm-svn: 43866
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- Nov 07, 2007
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Evan Cheng authored
llvm-svn: 43819
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Owen Anderson authored
llvm-svn: 43805
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- Nov 06, 2007
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Dan Gohman authored
llvm-svn: 43781
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Evan Cheng authored
When the allocator rewrite a spill register with new virtual register, it replaces other operands of the same register. Watch out for situations where only some of the operands are sub-register uses. llvm-svn: 43776
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Evan Cheng authored
llvm-svn: 43764
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Evan Cheng authored
llvm-svn: 43763
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Evan Cheng authored
other uses. There was a overly restricted check that prevented some obvious cases. llvm-svn: 43762
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Owen Anderson authored
llvm-svn: 43755
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Owen Anderson authored
llvm-svn: 43754
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Owen Anderson authored
llvm-svn: 43751
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Dan Gohman authored
llvm-svn: 43744
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Rafael Espindola authored
Thanks for the suggestions Bill :-) llvm-svn: 43742
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