Codegen bits and llvm-gcc support will follow.

llvm-svn: 44182

llvm-svn: 44181

llvm-svn: 44167

llvm-svn: 44166

llvm-svn: 44154

llvm-svn: 44153

to all targets uses GOT-relative offsets for PIC (Alpha?)

llvm-svn: 44108

MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.

llvm-svn: 44104

interference.

llvm-svn: 44064

llvm-svn: 44063

to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056

adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037

llvm-svn: 44019

llvm-svn: 44010

to be a pass of its own.  Instead, move it out into a helper method.

llvm-svn: 44002

llvm-svn: 43960

llvm-svn: 43944

apints on big-endian machines if the bitwidth is
not a multiple of 8.  Introduce a new helper,
MVT::getStoreSizeInBits, and use it.

llvm-svn: 43934

llvm-svn: 43933

Then:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        imull   $4, %ecx, %ecx
        leal    LJTI1_0-"L1$pb"(%eax), %edx
        addl    LJTI1_0-"L1$pb"(%ecx,%eax), %edx
        jmpl    *%edx

        .align  2
        .set L1_0_set_3,LBB1_3-LJTI1_0
        .set L1_0_set_2,LBB1_2-LJTI1_0
        .set L1_0_set_5,LBB1_5-LJTI1_0
        .set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

Now:
        call    "L1$pb"
"L1$pb":
        popl    %eax
		...
LBB1_1: # entry
        addl    LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
        jmpl    *%eax

		.align  2
		.set L1_0_set_3,LBB1_3-"L1$pb"
		.set L1_0_set_2,LBB1_2-"L1$pb"
		.set L1_0_set_5,LBB1_5-"L1$pb"
		.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
        .long    L1_0_set_3
        .long    L1_0_set_2

llvm-svn: 43924

llvm-svn: 43923

llvm-svn: 43922

llvm-svn: 43911

llvm-svn: 43910

If both parts of smul_lohi, etc. are used, don't simplify. If only one part is used, try simplify it.

llvm-svn: 43888

Add the majority of machine-level critical edge breaking pass.  Most of this was written by Fernando, cleanup and updating to TOT by me.

This still needs a bit of work, particularly to handle jump tables properly.

llvm-svn: 43885

llvm-svn: 43869

llvm-svn: 43866

llvm-svn: 43819

llvm-svn: 43805

llvm-svn: 43781

When the allocator rewrite a spill register with new virtual register, it replaces other operands of the same register. Watch out for situations where
only some of the operands are sub-register uses.

llvm-svn: 43776

llvm-svn: 43764

llvm-svn: 43763

other uses. There was a overly restricted check that prevented some obvious
cases.

llvm-svn: 43762

llvm-svn: 43755

llvm-svn: 43754

llvm-svn: 43751

llvm-svn: 43744

Thanks for the suggestions Bill :-)

llvm-svn: 43742