(isprofitable|islegal)tofold checks.

llvm-svn: 96331

IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255

produce a table based matcher instead of gobs of C++ Code.

Though it's not done yet, the shrinkage seems promising,
the table for the X86 ISel is 75K and still has a lot of 
optimization to come (compare to the ~1.5M of .o generated
the old way, much of which will go away).

The code is currently disabled by default (the #if 0 in
DAGISelEmitter.cpp).  When enabled it generates a dead
SelectCode2 function in the DAGISel Header which will
eventually replace SelectCode.

There is still a lot of stuff left to do, which are
documented with a trail of FIXMEs.

llvm-svn: 96215

This behaviour must be configurable.

llvm-svn: 96210

llvm-svn: 96199

on TreePatternNode to be methods on TreePatternNode.

llvm-svn: 96197

that predated -fast-isel which attempted to speed up the dag pattern
matchers at -O0.  Since fast-isel is around, this is basically 
obsolete and removing it shrinks the generated dag isels.

llvm-svn: 96188

llvm-svn: 96187

llvm-svn: 96186

Some tools do not like the '-option parameter' form. Should this be
configurable?

llvm-svn: 96130

class out of line.

llvm-svn: 96113

tables.

llvm-svn: 96073

llvm-svn: 96065

fix swapgs to be spelled right.

llvm-svn: 96058

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

whose opcodes extend into the ModR/M field using the
Form field of the instruction rather than by special
casing each instruction.  Commented out the special
casing of VMCALL, which is the first instruction to use
this special form.  While I was in the neighborhood,
added a few comments for people modifying the Intel
disassembler. 

llvm-svn: 96043

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

matcher is now free of implicit operands!
 - Still need to clean up the code now that we don't to worry about implicit
   operands, and to make it a hard error if an instruction fails to specify all
   of its operands for some reason.

llvm-svn: 95956

	testb	%al, %al                ## <MCInst #2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst #938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>

llvm-svn: 95935

llvm-svn: 95808

llvm-svn: 95802

 - Pretty messy, but we need to rework how we handle tied operands in MCInst
   anyway.

llvm-svn: 95774

backend to not use exceptions at all except in cases
of actual error.

llvm-svn: 95762

Disassembler to take advantage of the refactored
AsmWriterInst.h.  Note removed parser code.

llvm-svn: 95760

operand into the CodeGenInstruction's list of operands,
which is useful for EDEmitter.  (Still working on PR6219)

llvm-svn: 95759

for representing constraint info semantically instead of
as a c expression that will be blatted out to the .inc
file.  Fix X86RecognizableInstr to use this instead of
parsing C code :).

llvm-svn: 95753

implementation.  Also changed the constructor
so that it does not require a Record, making it
usable by the EDEmitter.

llvm-svn: 95715

it builds OK on Visual Studio.

llvm-svn: 95702

out of the AsmWriterEmitter.  This patch does the physical
code movement, but leaves the implementation unchanged. I'll
make any changes necessary to generalize the code in a
separate patch.

llvm-svn: 95697

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

llvm-svn: 95627

than DEBUG_VALUE :(  ) into the target indep AsmPrinter.cpp
file.   This allows elimination of the 
NO_ASM_WRITER_BOILERPLATE hack among other things.

llvm-svn: 95177

is still deterministic even amongst ambiguous instructions (eventually ambiguous
match orders will be a hard error, but we aren't there yet).

llvm-svn: 95157

in the order they were declared.

llvm-svn: 94868

disassembly information have a better comment (and
better guard macros).

llvm-svn: 94781

llvm-svn: 94776

enhanced disassembler, and the necessary makefile
rules to build the table for X86.

llvm-svn: 94764

llvm-svn: 94543

be static.  Also made it possible for clients to get it
and no other functions from ...GenAsmMatcher.inc by
defining REGISTERS_ONLY before including GenAsmMatcher.inc.
This sets the stage for target-specific lexers that can
identify registers and return AsmToken::Register as
appropriate.

llvm-svn: 94266

llvm-svn: 94261