Modify new MachineOperand so that its flags match the old MachineOperand's
 flags, for the flags that matter.

llvm-svn: 6513

by a re-link of TableGen will notify Make to rebuild the .inc file.

llvm-svn: 6512

llvm-svn: 6511

* Fix cast of (short|ushort|int|uint) to bool to work right

llvm-svn: 6510

llvm-svn: 6509

llvm-svn: 6507

llvm-svn: 6506

llvm-svn: 6503

llvm-svn: 6502

llvm-svn: 6499

llvm-svn: 6498

llvm-svn: 6496

llvm-svn: 6495

llvm-svn: 6486

Count resolutions correctly.

llvm-svn: 6482

llvm-svn: 6480

llvm-svn: 6479

llvm-svn: 6476

llvm-svn: 6470

TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.

llvm-svn: 6469

llvm-svn: 6468

preallocated.  While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.

llvm-svn: 6467

globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.

llvm-svn: 6466

call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465

llvm-svn: 6464

llvm-svn: 6463

llvm-svn: 6462

Created new classes from which instructions inherit their ordering of fields.

llvm-svn: 6461

* Fixed page numbers referring to the Sparc manual

llvm-svn: 6460

llvm-svn: 6459

llvm-svn: 6457

"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456

Fixed BasicBlock patching by supplying correct type for the displacement.

llvm-svn: 6453

llvm-svn: 6452

llvm-svn: 6451

* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers

llvm-svn: 6449

sections of instructions.

llvm-svn: 6448

For one, converting register numbers based on class in the code emitter.

llvm-svn: 6447

Code beautification for the rest of the code: changed layout to match the rest
of the code base.

llvm-svn: 6446

llvm-svn: 6444