llvm-svn: 72828

llvm-svn: 72825

llvm-svn: 72785

llvm-svn: 72775

Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.

llvm-svn: 72758

If there is a def of a super-register followed by a use of a sub-register, do *not* add an implicit def of the sub-register. e.g.
EAX = ..., AX<imp-def>
...
    = AX

This creates a double-def. Apparently this used to be necessary but is no longer needed.

Thanks to Anton for pointing this out. Anton, I cannot create a test case without your uncommitted ARM patches. Please check in a test case for me.

llvm-svn: 72755

one new .cpp file, in preparation for merging in the Direct Object Emission
changes we're working on. No functional changes.
Fixed coding style issues on the original patch. Patch by Aaron Gray

llvm-svn: 72754

llvm-svn: 72735

llvm-svn: 72729

llvm-svn: 72712

ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.

llvm-svn: 72707

llvm-svn: 72699

it is used both when a result is illegal and when an
operand is illegal.

llvm-svn: 72658

llvm-svn: 72650

JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray

llvm-svn: 72631

llvm-svn: 72604

llvm-svn: 72557

This patch removes some special cases for opcodes and does a bit of 
cleanup.

llvm-svn: 72536

llvm-svn: 72533

failure during llvm-gcc bootstrap:

Assertion failed: (!Tmp2.getNode() && "Can't legalize BR_CC with legal condition!"), function ExpandNode, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmCore.roots/llvmCore~obj/src/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 2923.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvmgcc42.roots/llvmgcc42~obj/src/gcc/libgcc2.c:1727: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.

llvm-svn: 72530

llvm-svn: 72516

This is basically the end of this series of patches for LegalizeDAG; the 
remaining special cases can't be removed without more infrastructure 
work.  There's a FIXME for each relevant opcode near the beginning of
SelectionDAGLegalize::LegalizeOp.

llvm-svn: 72514

some special cases are necessary.

llvm-svn: 72511

llvm-svn: 72509

Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.

llvm-svn: 72507

BUILD_VECTOR.

llvm-svn: 72469

llvm-svn: 72468

llvm-svn: 72467

llvm-svn: 72465

llvm-svn: 72464

llvm-svn: 72456

llvm-svn: 72455

llvm-svn: 72454

handling for every single opcode.

llvm-svn: 72447

entries as there are basic blocks in the function.  LiveVariables::getVarInfo
creates a VarInfo struct for every register in the function, leading to
quadratic space use.  This patch changes the BitVector to a SparseBitVector,
which doesn't help the worst-case memory use but does reduce the actual use in
very long functions with short-lived variables.

llvm-svn: 72426

llvm-svn: 72414

llvm-svn: 72411

bit clearer.

llvm-svn: 72374

corresponding integer type is legal.

llvm-svn: 72373

it's late, and I don't have any better ideas at the moment.  Fixes PR4257.

llvm-svn: 72363