A live range that has an early clobber tied redef now looks like a
normal tied redef, except the early clobber def uses the early clobber
slot.

This is enough to handle any strange interference problems.

llvm-svn: 149769

I don't have a test that fails because of this, but a test case like
CodeGen/X86/2009-12-01-EarlyClobberBug.ll exposes the problem.  EAX is
redefined by a tied early clobber operand on inline asm, and the live
range should look like this:

  %EAX,inf = [48r,64e:0)[64e,80r:1)  0@48r 1@64e

Previously, the two values got merged:

  %EAX,inf = [48r,80r:0)  0@48r

With this bug fixed, the REDEF_BY_EC VNInfo flag is no longer needed.

llvm-svn: 149768

Andy, in a previous commit you made this into an ImmutablePass so that you could
add it to the PassManager, then in the next commit you left it a Pass but
removed the code that added it to the PM. If you do add it to the PM then the PM
should take care of deleting it, but it's also true that nothing in codegen
needs this object to exist after it's done its work here. It's not clear to me
which design you want; this should likely either cease to be a Pass or be added
to the PM where other parts of CodeGen will request it.

llvm-svn: 149765

If a value is defined by a COPY, that instuction can easily and cheaply
be found by getInstructionFromIndex(VNI->def).

This reduces the size of VNInfo from 24 to 16 bytes, and improves
llc compile time by 3%.

llvm-svn: 149763

By default, boost the chain depth contribution of loads and stores. This will allow a load/store pair to vectorize even when it would not otherwise be long enough to satisfy the chain depth requirement.

llvm-svn: 149761

llvm-svn: 149758

add a blank line.

llvm-svn: 149757

It was writing generated files to the clang srcdir when
'--with-clang-srcdir' was specified.

llvm-svn: 149756

Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

llvm-svn: 149754

llvm-svn: 149753

llvm-svn: 149752

Left over from r116516.

llvm-svn: 149751

Don't form an out of bounds pointer just to test if it
would be out of bounds.

Also perform the same bounds checking for all the previous
mapped structures.

llvm-svn: 149750

Now this works with and without --with-clang-srcdir, with and
without an out-of-tree build.

llvm-svn: 149749

llvm-svn: 149737

llvm-svn: 149736

llvm-svn: 149732

llvm-svn: 149730

llvm-svn: 149728

They are not used any more. Simply use SlotIndex() to get an invalid
index.

llvm-svn: 149727

llvm-svn: 149724

llvm-svn: 149722

llvm-svn: 149717

llvm-svn: 149716

Calls that use register mask operands don't have implicit defs for
returned values.  The register mask operand handles the call clobber,
but it always behaves like a set of dead defs.

Add live implicit defs for any implicitly defined physregs that are
actually used.

llvm-svn: 149715

llvm-svn: 149714

When adding the {-1, -1} entry to the DFAStateInputTable, we
need to increment the index used to populate the DFAStateEntryTable.
Otherwise, the entry table will be off by one for each transition
after the {-1, -1} entry. PR11908.

llvm-svn: 149713

llvm-svn: 149712

llvm-svn: 149709

SelectionDAG has 4 different ways of passing physreg defs to users.
Collect all of the uses at the same time, and pass all of them to
MI->setPhysRegsDeadExcept() to mark the remaining defs dead.

The setPhysRegsDeadExcept() function will soon add the required
implicit-defs to instructions with register mask operands.

llvm-svn: 149708

llvm-svn: 149706

llvm-svn: 149705

llvm-svn: 149704

llvm-svn: 149698

The type-legalizer often scalarizes code. One of the common patterns is extract-and-truncate.
In this patch we optimize this pattern and convert the sequence into extract op of a narrow type.
This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases.

llvm-svn: 149692

llvm-svn: 149683

disassembler, just like the generic disassembler.

llvm-svn: 149681

Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.

llvm-svn: 149680

llvm-svn: 149678

llvm-svn: 149674