llvm-svn: 98124

llvm-svn: 98109

MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.

llvm-svn: 98098

MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.

llvm-svn: 98097

is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

llvm-svn: 98086

what fields of the CPSR or SPSR are affected.

llvm-svn: 98085

Make it so.  (This patch is in LowerCall_Darwin, which seems
to be used by SVR4 code as well; since that doesn't belong here,
I haven't worried about this case.)

llvm-svn: 98077

register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.

llvm-svn: 98071

Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.

llvm-svn: 98068

to an add or a sub.

llvm-svn: 98059

llvm-svn: 98058

llvm-svn: 98057

large code models.

llvm-svn: 98042

bear with the awful code. It won't last in its current state beyond tonight.

llvm-svn: 98040

llvm-svn: 98019

llvm-svn: 98018

llvm-svn: 98004

immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.

llvm-svn: 98001

for the encoding and is not the same as vmptrld.

llvm-svn: 97992

llvm-svn: 97982

This is a first step towards eliminating checks in Descriptor constructors.

llvm-svn: 97975

llvm-svn: 97963

inconsistent intrinsics.

llvm-svn: 97959

pattern which is broken (source and address swapped).

llvm-svn: 97958

llvm-svn: 97957

pattern, not i64.

llvm-svn: 97956

example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955

for, due to a bug.

llvm-svn: 97953

llvm-svn: 97950

This is a first step towards eliminating unncessary constructor checks in light weight DIDescriptor wrappers.

llvm-svn: 97947

could never have matched because the operand list was backwards.

llvm-svn: 97933

llvm-svn: 97891

llvm-svn: 97888

Patch by John Tytgat!

llvm-svn: 97886

We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.

llvm-svn: 97884

Do not use '&' prefix for globals when register base field is non-zero, otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).

This fixes PR6349

llvm-svn: 97877

llvm-svn: 97870

llvm-svn: 97869

registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.

llvm-svn: 97867

llvm-svn: 97818