Fixes PR18356.

llvm-svn: 198480

Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.

llvm-svn: 198475

Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.

This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.

With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.

llvm-svn: 198438

llvm-svn: 198437

llvm-svn: 198362

CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

llvm-svn: 198359

Several of the 64-bit fixed-point instructions with immediate operands were
using the 32-bit (i32) operand nodes instead of the corresponding 64-bit (i64)
operand definitions (u16imm instead of u16imm64, for example).

This error has had no effect so far, but would have caused type-checking
violations with an upcoming change.

llvm-svn: 198356

llvm-svn: 198336

Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.

llvm-svn: 198327

Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.

llvm-svn: 198323

llvm-svn: 198313

This patch makes it possible to select the ABI with -mattr. It will be used to
forward clang's -target-abi option to llvm's CodeGen.

llvm-svn: 198304

During the years there have been some attempts at figuring out how to
align byval arguments. A look at the commit log suggests that they
were

* Use the ABI alignment.
* When that was not sufficient for x86-64, I added the 's' specification to
  DataLayout.
* When that was not sufficient Evan added the virtual getByValTypeAlignment.
* When even that was not sufficient, we just got the FE to add the alignment
  to the byval.

This patch is just a simple cleanup that removes my first attempt at fixing the
problem. I also added an AArch64 implementation of getByValTypeAlignment to
make sure this patch is a nop. I also left the 's' parsing for backward
compatibility.

I will send a short email to llvmdev about the change for anyone maintaining
an out of tree target.

llvm-svn: 198287

llvm-svn: 198286

Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.

llvm-svn: 198284

llvm-svn: 198281

[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.

llvm-svn: 198280

llvm-svn: 198279

Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.

llvm-svn: 198278

Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277

Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198276

Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.

llvm-svn: 198265

llvm-svn: 198263

llvm-svn: 198262

llvm-svn: 198258

llvm-svn: 198257

llvm-svn: 198254

llvm-svn: 198241

Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198238

Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235

llvm-svn: 198201

llvm-svn: 198194

llvm-svn: 198193

llvm-svn: 198192

E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b

llvm-svn: 198188

The DPR and SPR register lists are also register lists.  Furthermore, the
registers need not be checked individually since the register type can be
checked via the list kind.  Use that to simplify the logic and fix the incorrect
assertion.

llvm-svn: 198174

In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

llvm-svn: 198172

llvm-svn: 198171

The vstm family of VFP instructions belong to the VFP store itinerary class, not
the VFP load itinerary class.

llvm-svn: 198170

llvm-svn: 198162