llvm-svn: 26729

llvm-svn: 26728

Regression/CodeGen/PowerPC/and_add.ll

a case that occurs with dynamic allocas of constant size.

llvm-svn: 26727

llvm-svn: 26725

llvm-svn: 26724

a select and FABS/FNEG.

This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.

llvm-svn: 26723

llvm-svn: 26722

llvm-svn: 26721

llvm-svn: 26720

1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719

to be emitted.

Don't add one to the latency of a completed instruction if the latency of the
op is 0.

llvm-svn: 26718

predecessor to finish before they can start.

llvm-svn: 26717

operands have all issued, but whose results are not yet available.  This
allows us to compile:

int G;
int test(int A, int B, int* P) {
   return (G+A)*(B+1);
}

to:

_test:
        lis r2, ha16(L_G$non_lazy_ptr)
        addi r4, r4, 1
        lwz r2, lo16(L_G$non_lazy_ptr)(r2)
        lwz r2, 0(r2)
        add r2, r2, r3
        mullw r3, r2, r4
        blr

instead of this, which has a stall between the lis/lwz:

_test:
        lis r2, ha16(L_G$non_lazy_ptr)
        lwz r2, lo16(L_G$non_lazy_ptr)(r2)
        addi r4, r4, 1
        lwz r2, 0(r2)
        add r2, r2, r3
        mullw r3, r2, r4
        blr

llvm-svn: 26716

which cycle it lands on.

llvm-svn: 26714

llvm-svn: 26713

is together, and direction independent code is together.

llvm-svn: 26712

merge succs/chainsuccs -> succs set

This has no functionality change, simplifies the code, and reduces the size
of sunits.

llvm-svn: 26711

llvm-svn: 26710

llvm-svn: 26709

llvm-svn: 26708

set construction, rather than intersecting various std::sets.  This reduces
the memory usage for the testcase in PR681 from 496 to 26MB of ram on my
darwin system, and reduces the runtime from 32.8 to 0.8 seconds on a
2.5GHz G5.  This also enables future code sharing between Dom and PostDom
now that they share near-identical implementations.

llvm-svn: 26707

llvm-svn: 26705

off the result string at the first null terminator.

llvm-svn: 26704

llvm-svn: 26703

llvm-svn: 26701

Perhaps llvm-db will turn into a read debugger someday.

llvm-svn: 26700

llvm-svn: 26697

llvm-svn: 26693

llvm-svn: 26692

llvm-svn: 26690

llvm-svn: 26689

llvm-svn: 26688

llvm-svn: 26687

llvm-svn: 26686

llvm-svn: 26684

llvm-svn: 26683

llvm-svn: 26682

keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up.  For something like this:

float testadd(float *X, float *Y, float *Z, float *W, float *V) {
  return (*X+*Y)*(*Z+*W)+*V;
}

For example, this makes us schedule *X then *Y, not *X then *Z.  The former
allows us to issue the add, the later only lets us issue other loads.

This turns the above code from this:

_testadd:
        lfs f0, 0(r3)
        lfs f1, 0(r6)
        lfs f2, 0(r4)
        lfs f3, 0(r5)
        fadds f0, f0, f2
        fadds f1, f3, f1
        lfs f2, 0(r7)
        fmadds f1, f0, f1, f2
        blr

into this:

_testadd:
        lfs f0, 0(r6)
        lfs f1, 0(r5)
        fadds f0, f1, f0
        lfs f1, 0(r4)
        lfs f2, 0(r3)
        fadds f1, f2, f1
        lfs f2, 0(r7)
        fmadds f1, f1, f0, f2
        blr

llvm-svn: 26680

priority impls that want to be notified when a node is scheduled

llvm-svn: 26678

llvm-svn: 26676