We used to generate a store (movq) + a load.
Now we use movd.

rdar://9946746

llvm-svn: 167056

llvm-svn: 167027

to test it with chapni's fix (-mattr=+avx).

llvm-svn: 166985

llvm-svn: 166979

llvm-svn: 166973

llvm-svn: 166972

%0 = load <8 x i16>* %dest
%1 = shufflevector <8 x i16> %0, <8 x i16> %in,
      <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
store <8 x i16> %1, <8 x i16>* %dest

We get:
  vmovlpd (%eax), %xmm0, %xmm0

instead of:
  vmovaps (%eax), %xmm1
  vmovsd  %xmm1, %xmm0, %xmm0

No extra test-case is added. I just fixed the existing one
(also it uses FileCheck now).

llvm-svn: 166971

equivalent to [expr1 + expr2].  See test cases for more examples.
rdar://12470392

llvm-svn: 166949

- Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled.

llvm-svn: 166947

llvm-svn: 166945

llvm-svn: 166922

All the credit goes to Jan Voung for noticing it was dead!

llvm-svn: 166902

llvm-svn: 166819

Part of rdar://12576868

llvm-svn: 166792

Part of rdar://12576868

llvm-svn: 166790

operator.

llvm-svn: 166779

llvm-svn: 166724

AsmParser logic.  To be used/tested in a subsequent commit.

llvm-svn: 166714

llvm-svn: 166698

llvm-svn: 166665

llvm-svn: 166664

[register].field

The operator returns the value at the location pointed to by register plus the
offset of field within its structure or union.  This patch only handles
immediate fields (i.e., [eax].4).  The original displacement has to be a
MCConstantExpr as well.
Part of rdar://12470415 and rdar://12470514

llvm-svn: 166632

llvm-svn: 166630

Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.

llvm-svn: 166593

see the offsetof operator.  Previously, we were matching something like MOVrm
in the front-end and later matching MOVrr in the back-end.  This change makes
things more consistent.  It also fixes cases where we can't match against a 
memory operand as the source (test cases coming).
Part of rdar://12470317

llvm-svn: 166592

This checkin also adds in some tests that utilize these paths and updates some of the
clients.

llvm-svn: 166578

llvm-svn: 166566

- As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to
  v2f32 is added to improve the efficiency of the code generated.

llvm-svn: 166545

the difference from "int x" (which should go in registers and
"struct y {int x;}" (which should not).

Clang will be updated in the next patches.

llvm-svn: 166536

pointer, not the size of the variable.
Part of rdar://12470317

llvm-svn: 166526

llvm-svn: 166525

non-zero value as we don't know the actual value at this point.  This is
necessary to get the matching correct in some cases.  However, the actual value
set as the base register doesn't matter, since we're just matching not emitting.

llvm-svn: 166523

and easier to read by adding a couple helper functions.  Suggestion by
Chandler Carruth and seconded by Meador Inge!

llvm-svn: 166515

- Check index being extracted to be constant 0 before simplfiying.
  Otherwise, retain the original sequence.

llvm-svn: 166504

llvm-svn: 166494

on patch to r166433.
rdar://12470317

llvm-svn: 166488

- Replace v4i8/v8i8 -> v8f32 DAG combine with custom lowering to reduce
  DAG combine overhead.
- Extend the support to v4i16/v8i16 as well.

llvm-svn: 166487

llvm-svn: 166486

Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm.  The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.

rdar://11764962

llvm-svn: 166445

Part of rdar://12470317

llvm-svn: 166436