There is no need to force an line number entry (using previous location) for a temp label at unknown location.

llvm-svn: 104740

usual suspects that could "return twice".

llvm-svn: 104737

MC: When running with -mc-relax-all, we can eagerly relax instructions and avoid creating unnecessary MCInstFragments.

llvm-svn: 104736

MC/Mach-O: Factor out EmitInstTo{Fragment,Data} for emitting MCInst's as MCInstFragments or appending onto an MCDataFragment.

llvm-svn: 104735

ISD::. No functional change.

llvm-svn: 104734

llvm-svn: 104732

llvm-svn: 104731

more than just the stack slot coloring algorithm.

llvm-svn: 104722

Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope().

llvm-svn: 104720

implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718

llvm-svn: 104717

llvm-svn: 104716

llvm-svn: 104713

llvm-svn: 104711

Reduced from one provided by Duncan Sands, thanks!

llvm-svn: 104710

llvm-svn: 104709

before encoding.

llvm-svn: 104707

llvm-svn: 104706

llvm-svn: 104705

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

llvm-svn: 104703

llvm-svn: 104699

llvm-svn: 104698

llvm-svn: 104697

llvm-svn: 104696

llvm-svn: 104692

llvm-svn: 104691

llvm-svn: 104689

llvm-svn: 104670

Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667

llvm-svn: 104664

llvm-svn: 104661

This reverts commit 104654.

llvm-svn: 104660

base class, since all the implementations are the same.

llvm-svn: 104659

llvm-svn: 104658

llvm-svn: 104657

machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653

Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652