[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.

llvm-svn: 198280

llvm-svn: 198279

Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.

llvm-svn: 198278

Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277

Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198276

Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.

llvm-svn: 198265

llvm-svn: 198263

llvm-svn: 198262

llvm-svn: 198258

llvm-svn: 198257

llvm-svn: 198254

llvm-svn: 198241

Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.

llvm-svn: 198238

Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235

llvm-svn: 198201

llvm-svn: 198194

llvm-svn: 198193

llvm-svn: 198192

E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b

llvm-svn: 198188

The DPR and SPR register lists are also register lists.  Furthermore, the
registers need not be checked individually since the register type can be
checked via the list kind.  Use that to simplify the logic and fix the incorrect
assertion.

llvm-svn: 198174

In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

llvm-svn: 198172

llvm-svn: 198171

The vstm family of VFP instructions belong to the VFP store itinerary class, not
the VFP load itinerary class.

llvm-svn: 198170

llvm-svn: 198162

This plugs a memory leak in ARM's FastISel by storing the GV in Module so that
it's reclaimed.
PR17978

llvm-svn: 198160

[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
 This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157

[SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().
 This makes the sparc backend to generate Sparc64 ABI compliant code.

llvm-svn: 198149

llvm-svn: 198146

Also, pass fp128 arguments to varargs through integer registers if necessary.

llvm-svn: 198145

llvm-svn: 198144

Directive parsers must return false if the target assembler is interested in
handling the directive.  The Error member function returns true always.  Using
the 'return Error()' pattern would incorrectly indicate to the general parser
that the target was not interested in the directive, when in reality it simply
encountered a badly formed directive or some other error.  This corrects the
behaviour to ensure that the parser behaves appropriately.

llvm-svn: 198132

Schedule more conservatively to account for stalls on floating point
resources and latency. Use the AGU resource to model latency stalls
since it's shared between FP and LD/ST instructions. This might not be
completely accurate but should work well in practice.

llvm-svn: 198125

Many vector operations never had itineraries. Since the new machine
model was a mapping from existing itinerary classes, we don't have a
model for these. We still want to migrate A9 even though no one has
invested in a complete model, so mark it incomplete to avoid the
scheduler asserting.

llvm-svn: 198123

Factor the MachineFunctionPass into MachineSchedulerBase.

Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive.

llvm-svn: 198119

llvm-svn: 198117

Minor indentation fix to match other switch statements. Change llvm_unreachable text to match similar places.

llvm-svn: 198116

vector shift by immedate count (VSHLI/VSRLI/VSRAI) into a build_vector when
the vector in input to the shift is a build_vector of all constants or UNDEFs.

Target specific nodes for packed shifts by immediate count are in
general introduced by function 'getTargetVShiftByConstNode' (in
X86ISelLowering.cpp) when lowering shift operations, SSE/AVX immediate
shift intrinsics and (only in very few cases) SIGN_EXTEND_INREG dag
nodes.

This patch adds extra rules for simplifying vector shifts inside
function 'getTargetVShiftByConstNode'.

Added file test/CodeGen/X86/vec_shift5.ll to verify that packed
shifts by immediate are correctly folded into a build_vector when the
input vector to the shift dag node is a vector of constants or undefs.

llvm-svn: 198113

llvm-svn: 198095

widespread glibc bugs.

The glibc implementation of exp10 has a very serious precision bug in
version 2.15 (and older versions). This is still very widely used (the
current Ubuntu LTS for example uses it) and so it isn't reasonable to
make transforms that produce these functions. This fixes many
miscompiles introduced when we started transforming pow(10.0, ...) into
exp10, and it may have fixed other latent miscompiles where exp10
provided sufficient precision but exp10f did not.

This is all really horrible. The primary bug has been fixed for over
a year and glibc 2.18 works correctly for the test cases I have, but it
will be 2017 before the LTS using 2.15 is no longer supported by Ubuntu
(and thus reasonable for folks to be relying on). =[ We're either going
to need to live without these optimizations, or find a way to switch
behavior more dynamically than using simply the fact that the OS is
"Linux".

To make matters worse, there appears to be significant testing and
fixing of numerous other bugs in the exp10 family of functions right now
in glibc. While those haven't been causing problems I've seen in the
wild, it gives me concerns that we may need to wait until an even later
release of glibc before we can reliably transform code into exp10.

llvm-svn: 198093

This makes it unavailable on NetBSD, Android, etc.

Patch by Brad Smith!

llvm-svn: 198056