llvm-svn: 27473

llvm-svn: 27471

llvm-svn: 27470

llvm-svn: 27469

Convert vsldoi(x,x) to work the same way other (x,x) cases work.

llvm-svn: 27467

llvm-svn: 27463

llvm-svn: 27460

llvm-svn: 27457

llvm-svn: 27453

lower it and LLVM to have one fewer intrinsic.  This implements
CodeGen/PowerPC/vec_shuffle.ll

llvm-svn: 27450

vperm with a perm mask lvx'd from the constant pool.

llvm-svn: 27448

llvm-svn: 27446

llvm-svn: 27445

llvm-svn: 27444

llvm-svn: 27442

llvm-svn: 27440

llvm-svn: 27439

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27434

llvm-svn: 27433

llvm-svn: 27427

llvm-svn: 27425

llvm-svn: 27423

llvm-svn: 27421

llvm-svn: 27419

llvm-svn: 27418

llvm-svn: 27417

llvm-svn: 27416

llvm-svn: 27414

Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.

llvm-svn: 27413

llvm-svn: 27412

llvm-svn: 27410

llvm-svn: 27405

handle all 4 PPC vector types.   This simplifies the matching code and allows
us to eliminate a bunch of patterns.  This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.

llvm-svn: 27400

llvm-svn: 27393

llvm-svn: 27388

llvm-svn: 27387

llvm-svn: 27386

llvm-svn: 27385

llvm-svn: 27384