with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.

llvm-svn: 68576

llvm-svn: 68569

Right now DBG_LABEL are required for llvm.dbg.region_start and llvm.dbg.region_end in non-fast mode also.

llvm-svn: 68559

SelectionDAG do those. This fixes PR3955.

llvm-svn: 68546

loads when an input node has multiple uses.

llvm-svn: 68398

Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.

llvm-svn: 68355

To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize.

llvm-svn: 68329

llvm-svn: 68134

entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.

llvm-svn: 68129

llvm-svn: 68113

llvm-svn: 68099

Remove the "fast" cases for spill and restore point determination, as these were subtlely wrong in obscure cases.  Patch the testcase
to account for this change.

llvm-svn: 68093

llvm-svn: 68092

instructions. This fixes lua.

llvm-svn: 68083

Turn a 2-address instruction into a 3-address one when it's profitable even if the two-address operand is killed.
e.g.
%reg1024<def> = MOV r1
%reg1025<def> = ADD %reg1024, %reg1026
r0            = MOV %reg1025

If it's not possible / profitable to commute ADD, then turning ADD into a LEA saves a copy.

llvm-svn: 68065

llvm-svn: 68059

llvm-svn: 68057

llvm-svn: 68054

when using -soft-float.
Based on a patch by Jakob Stoklund Olesen.

llvm-svn: 67996

a CALL and a RET node more generic. Add a test for tail calls with a void
return.

llvm-svn: 67943

Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).

llvm-svn: 67934

Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax

llvm-svn: 67917

llvm-svn: 67881

default constructor produces an uninitialized APInt.
This fixes PR3896.

llvm-svn: 67879

llvm-svn: 67828

llvm-svn: 67764

llvm-svn: 67742

Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.

llvm-svn: 67701

stoppoint nodes around until Legalize; doing this
imposed an ordering on a sequence of loads that
came from different lines, interfering with scheduling.

llvm-svn: 67692

llvm-svn: 67668

llvm-svn: 67661

llvm-svn: 67649

the target constraint specifies a specific physreg.

llvm-svn: 67618

llvm-svn: 67617

fail.

llvm-svn: 67616

canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.

llvm-svn: 67587

help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.

llvm-svn: 67586

llvm-svn: 67580

Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.                                                                                                  
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.

llvm-svn: 67574

same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562