llvm-svn: 57780

llvm-svn: 57779

 - Support noreturn on function-typed variables.

 - Extend isFunctionOrMethod to return true for K&R functions and
   provide hasFunctionProto to check if a decl has information about
   its arguments. This code needs some serious cleaning, but works.

 - Add/improve test cases for noreturn and unused.

llvm-svn: 57778

llvm-svn: 57777

llvm-svn: 57775

Patch by Timo Sirainen!

llvm-svn: 57772

the previous patch this one actually passes make check.

"Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand."

llvm-svn: 57771

llvm-svn: 57770

for Obj-C methods.

llvm-svn: 57769

llvm-svn: 57766

llvm-svn: 57765

llvm-svn: 57764

Generalize VisitLValue: not only can CallExprs and ObjCMessageExprs return aggregate temporaries, so can many other expressions.

llvm-svn: 57761

Function calls and ObjC message expressions can be used in a lvalue context if they return a structure.  E.g  foo().x == 1.  We don't really support, however, such temporaries yet in the environment or the store.

llvm-svn: 57760

retain/release checker: Check if a tracked value escapes if we also try binding it to the store and the store doesn't support that binding (i.e., it cannot track it).  This has the nice feature that the checker will automatically get more powerful if we use a more powerful store model.

llvm-svn: 57755

Use "VisitLValue" when processing the base for "x.f" field accesses, and "Visit" when processing the base for "x->f" field accesses.

llvm-svn: 57754

llvm-svn: 57751

llvm-svn: 57750

llvm-svn: 57749

and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748

test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.

llvm-svn: 57747

No functionality change.

llvm-svn: 57746

llvm-svn: 57745

llvm-svn: 57744

llvm-svn: 57743

llvm-svn: 57742

Hack: have BasicStore::getLValueElement return the "Base" lvalue.  This restores null dereference checking with array accesses.

BasicStore::RemoveDeadBindings: handle regions besides VarRegions (we now have FieldRegions).

llvm-svn: 57741

When conjuring symbols to recover path-sensitivity, don't conjure symbols that represent an entire struct.  We need to implement struct temporaries as an actual "region", and then bind symbols to the FieldRegion of those temporaries.

llvm-svn: 57739

 - Shouldn't assume predefined expr is a function printing one.
 - Uses CGM functionality to cache function names per module.

llvm-svn: 57737

(first) global holding the string.
 - No functionality change.

llvm-svn: 57736

llvm-svn: 57735

llvm-svn: 57734

llvm-svn: 57733

llvm-svn: 57731

Enhance "Assumption" logic in BasicConstraintManager when reasoning about regions and symbolic regions.  When assuming whether or not a location is non-null, walk up the region hierarchy until we hit a symbolic region (and test it for null).  This may not be the end all solution, as the notion of what a "symbolic region" is really belongs in the specific subclass of StoreManager.

llvm-svn: 57730

ISD condition opcodes into helper functions.

llvm-svn: 57726

llvm-svn: 57724

Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.

llvm-svn: 57723

Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.

TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722

assert.

llvm-svn: 57721