If a value is defined by a COPY, that instuction can easily and cheaply
be found by getInstructionFromIndex(VNI->def).

This reduces the size of VNInfo from 24 to 16 bytes, and improves
llc compile time by 3%.

llvm-svn: 149763

By default, boost the chain depth contribution of loads and stores. This will allow a load/store pair to vectorize even when it would not otherwise be long enough to satisfy the chain depth requirement.

llvm-svn: 149761

llvm-svn: 149758

add a blank line.

llvm-svn: 149757

Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

llvm-svn: 149754

llvm-svn: 149753

llvm-svn: 149752

Don't form an out of bounds pointer just to test if it
would be out of bounds.

Also perform the same bounds checking for all the previous
mapped structures.

llvm-svn: 149750

llvm-svn: 149737

llvm-svn: 149736

llvm-svn: 149732

llvm-svn: 149730

llvm-svn: 149724

llvm-svn: 149722

llvm-svn: 149717

llvm-svn: 149716

Calls that use register mask operands don't have implicit defs for
returned values.  The register mask operand handles the call clobber,
but it always behaves like a set of dead defs.

Add live implicit defs for any implicitly defined physregs that are
actually used.

llvm-svn: 149715

llvm-svn: 149714

llvm-svn: 149712

llvm-svn: 149709

SelectionDAG has 4 different ways of passing physreg defs to users.
Collect all of the uses at the same time, and pass all of them to
MI->setPhysRegsDeadExcept() to mark the remaining defs dead.

The setPhysRegsDeadExcept() function will soon add the required
implicit-defs to instructions with register mask operands.

llvm-svn: 149708

llvm-svn: 149706

llvm-svn: 149705

llvm-svn: 149704

llvm-svn: 149698

The type-legalizer often scalarizes code. One of the common patterns is extract-and-truncate.
In this patch we optimize this pattern and convert the sequence into extract op of a narrow type.
This allows the BUILD_VECTOR dag optimizations to construct efficient shuffle operations in many cases.

llvm-svn: 149692

llvm-svn: 149683

Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.

llvm-svn: 149680

llvm-svn: 149678

Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

llvm-svn: 149672

llvm-svn: 149671

needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668

llvm-svn: 149655

llvm-svn: 149650

llvm-svn: 149649

More targetted fix replacing d0e277d272d517ca1cda368267d199f0da7cad95.

llvm-svn: 149648

This reverts commit d0e277d272d517ca1cda368267d199f0da7cad95.

llvm-svn: 149647

It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646

NEON loads and stores accept single and double spaced pairs, triples,
and quads of D registers.  This patch adds new register classes to
accurately model those constraints:

  Dn, Dn+1    Dn, Dn+2
  ----------------------
  DPair       DPairSpc
  DTriple     DTripleSpc
  DQuad       DQuadSpc

Also extend the existing QQ and QQQQ register classes to contains all Q
pairs and quads instead of just the aligned ones.

These new register classes will make it possible to accurately model
constraints on NEON loads and stores, and we can get rid of all the NEON
pseudo-instructions.  The late scheduler will be able to accurately
model instruction dependencies from the explicit operands.

This more than doubles the number of ARM registers, but the backend
passes are quite good at handling this. The llc -O0 compile time only
regresses by 1.5%.  Future work on register mask operands will recover
this regression.

llvm-svn: 149640

Also silences warnings about bodyless for loops.

llvm-svn: 149612