llvm-svn: 31690

llvm-svn: 31684

potentially some system calls/exception handling from working.  TOS must always
link to previous frame.  This is a short term workaround until alloca scheme is
reworked.

llvm-svn: 31677

llvm-svn: 31676

llvm-svn: 31674

produces this clever code:

_millisecs:
        lis r2, ha16(_Time.1182)
        lwzu r3, lo16(_Time.1182)(r2)
        lwz r2, 4(r2)
        addic r4, r2, 1
        addze r3, r3
        blr

instead of this:

_millisecs:
        lis r2, ha16(_Time.1182)
        la r3, lo16(_Time.1182)(r2)
        lwz r2, lo16(_Time.1182)(r2)
        lwz r3, 4(r3)
        addic r4, r3, 1
        addze r3, r2
        blr

for:

long %millisecs() {
        %tmp = load long* %Time.1182            ; <long> [#uses=1]
        %tmp1 = add long %tmp, 1                ; <long> [#uses=1]
        ret long %tmp1
}

llvm-svn: 31673

globals.

llvm-svn: 31672

llvm-svn: 31656

llvm-svn: 31654

llvm-svn: 31650

llvm-svn: 31649

take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.

This fixes PR996.

llvm-svn: 31645

SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.

llvm-svn: 31641

llvm-svn: 31637

llvm-svn: 31634

llvm-svn: 31633

(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.

llvm-svn: 31621

llvm-svn: 31617

Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.

llvm-svn: 31616

This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).

llvm-svn: 31613

llvm-svn: 31612

llvm-svn: 31599

llvm-svn: 31596

llvm-svn: 31595

remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592

llvm-svn: 31583

llvm-svn: 31576

llvm-svn: 31572

llvm-svn: 31571

TODO: fix lea_addri

llvm-svn: 31552

This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.

llvm-svn: 31542

class, where it can be used for preinc formation.

llvm-svn: 31536

llvm-svn: 31535

shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.

Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>

llvm-svn: 31519

llvm-svn: 31506

llvm-svn: 31485

llvm-svn: 31477

llvm-svn: 31464

llvm-svn: 31463

llvm-svn: 31462