XFAIL this test.  It only worked before because of a bug in the spill point selection code.  Not deleting because 
it should be possible to enhance the selection code to handle this in the future.

llvm-svn: 63340

Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins.

llvm-svn: 63323

the element indices may be equal if either one is not a
constant.

llvm-svn: 63311

llvm-svn: 63304

llvm-svn: 63300

llvm-svn: 63267

dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266

llvm-svn: 63252

llvm-svn: 63247

llvm-svn: 63244

Do not forget to derived type while constructing an array type.

llvm-svn: 63233

after the others.

llvm-svn: 63227

llvm-svn: 63222

The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.

llvm-svn: 63195

llvm-svn: 63194

Adds new option properties 'multi_val', 'one_or_more' and 'zero_or_one'.

llvm-svn: 63172

llvm-svn: 63149

llvm-svn: 63090

llvm-svn: 63089

to help verify that the feature may be disabled through
the -mno-red-zone option.

llvm-svn: 63079

Assorted debug info fixes.
- DW_AT_bit_size is only suitable for bitfields.
- Encode source location info for derived types.
- Source location and type size info is not useful for subroutine_type (info is included in respective DISubprogram) and array_type.

llvm-svn: 63077

llvm-svn: 63075

llvm-svn: 63067

checking logic.  Rather than make the checking more
complicated, I've tweaked some logic to make things
conform to how the checking thought things ought to
be, since this results in a simpler "mental model".

llvm-svn: 63048

llvm-svn: 63042

Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start.

llvm-svn: 63022

has a different number of elements than the output.

llvm-svn: 62998

- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>

llvm-svn: 62990

llvm-svn: 62985

handling the flaw inherent in that assumption.  :)

llvm-svn: 62984

other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980

for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972

llvm-svn: 62969

llvm-svn: 62967

llvm-svn: 62957

llvm-svn: 62956

llvm-svn: 62955

Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1028                                                                                                                                            
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>                                                                                                         

In this case, it might not be possible to coalesce the second MOV8rr                                                                                                                 
instruction if the first one is coalesced. So it would be profitable to                                                                                                              
commute it:                                                                                                                                                                          
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1029                                                                                                                                            
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>

llvm-svn: 62954

llvm-svn: 62921

Also it was an empty struct, not a void after all.

llvm-svn: 62920