llvm-svn: 90172

New virtual registers created for spill intervals should inherit allocation hints from the original register.

This helps us avoid silly copies when rematting values that are copied to a physical register:

leaq	_.str44(%rip), %rcx
movq	%rcx, %rsi
call	_strcmp

becomes:

leaq	_.str44(%rip), %rsi
call	_strcmp

The coalescer will not touch the movq because that would tie down the physical register.

llvm-svn: 90163

branches even when optimizing for code size.  Unless we find evidence to the
contrary in the future, the special treatment for indirect branches does not
have a significant effect on code size, and performance still matters with -Os.

llvm-svn: 90147

for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144

llvm-svn: 90136

llvm-svn: 90134

llvm-svn: 90133

divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.

llvm-svn: 90108

llvm-svn: 89968

llvm-svn: 89905

running tail duplication when doing branch folding for if-conversion, and
we also want to be able to run tail duplication earlier to fix some
reg alloc problems.  Move the CanFallThrough function from BranchFolding
to MachineBasicBlock so that it can be shared by TailDuplication.

llvm-svn: 89904

ProcessImplicitDefs should watch out for invalidated iterator and extra implicit operands on copies.

llvm-svn: 89880

llvm-svn: 89873

llvm-svn: 89866

Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation.  I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size.  ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.

llvm-svn: 89814

llvm-svn: 89793

llvm-svn: 89790

llvm-svn: 89787

llvm-svn: 89725

<rdar://problem/6721894>. Allow multiple registers to be renamed together (super and sub) if necessary to break an anti-dependence.

llvm-svn: 89722

Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711

llvm-svn: 89702

no filename. This situation is apparently fairly common right now.

llvm-svn: 89701

llvm-svn: 89686

llvm-svn: 89683

SelectionDAGBuild.cpp to SelectionDAGBuilder.cpp.

llvm-svn: 89681

in this file.

llvm-svn: 89675

FunctionLoweringInfo.cpp.

llvm-svn: 89674

llvm-svn: 89671

of SelectionDAGBuild.h/cpp into its own files, to help separate
general lowering logic from SelectionDAG-specific lowering logic.

llvm-svn: 89667

llvm-svn: 89645

tell debug info which base register to use to reference a frame index on a
per-index basis. This is useful, for example, in the presence of dynamic
stack realignment when local variables are indexed via the stack pointer and
stack-based arguments via the frame pointer.

llvm-svn: 89620

llvm-svn: 89612

Teach MachineBasicBlock::updateTerminator() to handle a failing TII->ReverseBranchCondition(Cond) call.

This fixes the MallocBench/cfrac test case regression.

llvm-svn: 89608

llvm-svn: 89567

Allow target to disable if-converting predicable instructions. e.g. NEON instructions under ARM mode.

llvm-svn: 89541

llvm-svn: 89537

llvm-svn: 89536

When splitting a critical edge, the registers live through the edge are:

- Used in a PHI instruction, or
- Live out from the predecessor, and
- Live in to the successor.

This allows the coalescer to eliminate even more phi joins.

llvm-svn: 89530

llvm-svn: 89522