rounding the stack frame to a multiple of stack alignment.

llvm-svn: 33504

PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.

llvm-svn: 33460

llvm-svn: 33396

We not align the final stack slot but instead let the target do so in emitPrologue(). Each target can make adjustments to the stack frame and re-align the stack as it deem appropriate. Do not align it twice which can end up wasting stack space.

llvm-svn: 33387

- Make use of spillCalleeSavedRegisters() and restoreCalleeSavedRegisters().

llvm-svn: 32822

llvm-svn: 32299

TargetRegisterClass specifies the desired spill alignment. However, it cannot be honored if stack alignment is smaller.

llvm-svn: 30648

incoming stack. This allows X86 backend to use push / pop in epilogue /
prologue.

llvm-svn: 30636

llvm-svn: 30616

llvm-svn: 29911

llvm-svn: 29888

information and exception handling.

llvm-svn: 29881

llvm-svn: 28973

llvm-svn: 28253

llvm-svn: 27491

llvm-svn: 27380

llvm-svn: 24227

alignment information appropriately.  Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack.  Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224

llvm-svn: 23559

class into the spill/reload methods.  Targets can now rely on that argument.

llvm-svn: 23556

code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.

llvm-svn: 23536

Olden/bisort among others.

llvm-svn: 23124

llvm-svn: 23108

terminator instructions before the 'ret' in case the target has a
multi-instruction return sequence.

llvm-svn: 22041

llvm-svn: 21982

llvm-svn: 21420

registers.  This information is computed directly by the register allocator
now.

llvm-svn: 19795

llvm-svn: 19787

This fixes the return-address-not-being-saved problem in the Alpha backend.

llvm-svn: 19741

llvm-svn: 19704

Put this change back in after testing from Reid proved its innocence.  getSpillSize now returns value in bits

llvm-svn: 16102

Back out change to divide getSpillSize by 8 until I figure out why it breaks x86, which has register sizes in bits.

llvm-svn: 16073

llvm-svn: 16070

bytes.

llvm-svn: 15970

of getRegClass

llvm-svn: 15967

llvm-svn: 15775

llvm-svn: 15774

allowed).

llvm-svn: 15766

llvm-svn: 15736

Add support for targets that must spill certain physregs at certain locations.

Patch contributed by Nate Begeman, slightly hacked by me.

llvm-svn: 15701