ask instructions for their parent.

llvm-svn: 14998

llvm-svn: 14997

llvm-svn: 14996

* vreg <-> vreg joining now works, enable it unconditionally when joining
  is enabled (which is the default).
* Fix a serious pessimization of spill code where we were saying that a
  spilled DEF operand was live into the subsequent instruction.  This allows
  for substantially better code when spilling starts to happen.

llvm-svn: 14993

order, causing the inactive list in the linearscan list to get unsorted, which
basically fuxored everything up severely.

These seems to fix the joiner, so with more testing I will enable it by default.

llvm-svn: 14992

llvm-svn: 14991

is sorted.  This is not the case currently, which is causing no end of
problems.

llvm-svn: 14990

Heavily refactor handleVirtualRegisterDef, adding comments and making it more
efficient.  It is also much easier to follow and convince ones self that it is
correct :)

Add -debug output to the joine, showing the result of joining the intervals.

llvm-svn: 14989

remove map that is not needed

llvm-svn: 14988

but make virtreg->virtreg joining stay off by default

llvm-svn: 14916

llvm-svn: 14866

llvm-svn: 14865

llvm-svn: 14845

llvm-svn: 14725

* Fix spacing, grammar in comment
* Make code layout consistent
* Wrap code at 80 cols
* Delete spurious blank lines

No functional changes.

llvm-svn: 14721

llvm-svn: 14720

llvm-svn: 14719

llvm-svn: 14679

llvm-svn: 14655

classes: just ignore that move. Thanks to Vladimir Prus who found the
bug!

llvm-svn: 14644

basic block clear()'s all of the operands lists, including phis.  This
caused removePredecessor to get confused later.  Because of this, we just
nuke (without prejudice) PHI nodes in unreachable blocks.

llvm-svn: 14635

llvm-svn: 14626

llvm-svn: 14622

llvm-svn: 14590

don't exist, we don't have to pretend to handle them.

llvm-svn: 14567

pass is required to paper over problems in the code generator (primarily
live variables and its clients) which doesn't really have any well defined
semantics for unreachable code.

The proper solution to this problem is to have instruction selectors not
select blocks that are unreachable.  Until we have a instruction selection
framework available for use, however, we can't expect all instruction
selector writers to do this.  Until then, this pass should be used.

llvm-svn: 14563

any other data structures

llvm-svn: 14524

use them instead of a local LiveVariables numbering

llvm-svn: 14523

mapping

llvm-svn: 14521

llvm-svn: 14520

map.

llvm-svn: 14518

Also convert df_iterator -> df_ext_iterator for subsequent stuff I'm doing.

llvm-svn: 14517

llvm-svn: 14475

llvm-svn: 14474

instructions.  Instead, keep a map of instructions -> MCFI objects in the
already sparc-specific class MachineFunctionInfo.  This will slow down the
sparc backend a bit, but it does not penalize the rest of LLVM!

llvm-svn: 14438

Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.

llvm-svn: 14389

llvm-svn: 14373

move InstructionLowering itself.

llvm-svn: 14324

IntrinsicLowering, for instance).

llvm-svn: 14323

existing llvm::Interval class.

Patch contributed by Vladimir Prus!
http://mail.cs.uiuc.edu/pipermail/llvmbugs/2004-June/000710.html

llvm-svn: 14281