llvm-svn: 154889

llvm-svn: 154881

llvm-svn: 154706

Fix target specific intrinsic handling to adjust intrinsic number before doing attribute table lookup. Also fix attribute table lookup to handle 'invalid' intrinsic correctly. Fixes PR12542

llvm-svn: 154658

llvm-svn: 154533

llvm-svn: 154532

llvm-svn: 154531

llvm-svn: 154518

The pruning is more complete if it is not done incrementally. The code
is also a tad less convluted.

llvm-svn: 154510

llvm-svn: 154477

Handle mixing allocatable and unallocatable register gracefully.
Simplify the pruning of register unit sets.

llvm-svn: 154474

llvm-svn: 154452

Recent refactoring introduced a bug. Fix: added buildRegUnitSets.

llvm-svn: 154382

Jakob's review.

llvm-svn: 154377

This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.

llvm-svn: 154374

This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.

llvm-svn: 154373

llvm-svn: 154372

llvm-svn: 154070

llvm-svn: 153997

svn r145378 inadvertently changed the destination for the Embedded target
in the makefile.  Add a "/Developer" suffix to DSTROOT to compensate.

llvm-svn: 153980

llvm-svn: 153978

llvm-svn: 153977

So far all of configure tests have been run against the default SDK and
architecture, regardless of what is actually being built.  We've gotten
lucky until now.  <rdar://problem/11112479>

llvm-svn: 153972

llvm-svn: 153971

llvm-svn: 153937

llvm-svn: 153935

As Eric pointed out, even a Debug build should be equal. Leave the flag that can turn off comparisons though.

llvm-svn: 153927

llvm-svn: 153922

I just noticed Jakob's examples of the proper application of
std::set... routines.

llvm-svn: 153918

llvm-svn: 153909

llvm-svn: 153875

This way we can get AVX v-prefixed instructions tail merged with the normal insns.

llvm-svn: 153869

Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree.

llvm-svn: 153865

Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.

llvm-svn: 153863

llvm-svn: 153857

Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.

llvm-svn: 153841

This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

llvm-svn: 153837

llvm-svn: 153796

First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

llvm-svn: 153794

It's slow, bloated and completely redundant with MCRegisterClass::contains.

llvm-svn: 153782