Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form.

llvm-svn: 186897

llvm-svn: 186893

llvm-svn: 186892

llvm-svn: 186890

llvm-svn: 186886

llvm-svn: 186885

When we vectorize across multiple basic blocks we may vectorize PHINodes that create a cycle. We already break the cycle on phi-nodes, but arithmetic operations are still uplicated. This patch adds code that checks if the operation that we are vectorizing was vectorized during the visit of the operands and uses this value if it can.

llvm-svn: 186883

llvm-svn: 186880

llvm-svn: 186879

absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878

llvm-svn: 186877

[stackprotector] Changed isNoopBitcast/sameNoopInput to take TargetLoweringBase instead of TargetLowering.

Both functions only use functionality from TargetLoweringBase.

rdar://13935163

llvm-svn: 186874

Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.

llvm-svn: 186869

No functionality change.

rdar://13935163

llvm-svn: 186868

Instead of just adding the scope to the list, we actually handle the scope.

llvm-svn: 186867

 Use the function attributes to pass along the stack protector buffer size.

 Now that we have robust function attributes, don't use a command line option to
 specify the stack protecto buffer size.

llvm-svn: 186863

Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861

llvm-svn: 186858

the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855

llvm-svn: 186851

Fix an obvious typo in the loop vectorizer where the cost model uses the wrong variable. The variable BlockCost is ignored.
We don't have tests for the effect of if-conversion loops because it requires a big test (that includes if-converted loops) and it is difficult to find and balance a loop to do the right thing.

llvm-svn: 186845

llvm-svn: 186844

Option aliases in option groups were previously disallowed by an assert.
As far as I can tell, there was no technical reason for this, and I would
like to be able to put cl.exe compatible options in their own group for Clang,
so let's change the assert.

llvm-svn: 186838

instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

llvm-svn: 186831

.ftz to instructions if the nvptx-f32ftz attribute is set to "true"

llvm-svn: 186820

This reverts commit r186813, which broke the bots.

llvm-svn: 186818

llvm-svn: 186815

llvm-svn: 186814

llvm-svn: 186813

llvm-svn: 186812

llvm-svn: 186811

After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.

llvm-svn: 186810

llvm-svn: 186809

llvm-svn: 186808

Added missing - in the header of PrologEpilogInserter.h so that editors properly realize it is a c++ header and not a c header.

llvm-svn: 186801

deallocation functions.

llvm-svn: 186798

llvm-svn: 186790

to iterate over.

llvm-svn: 186788

llvm-svn: 186787

llvm-svn: 186786