llvm-svn: 137090

Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074

llvm-svn: 137073

They improve the verbose assembly.

llvm-svn: 137069

llvm-svn: 137067

Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.

llvm-svn: 137064

These the methods are target-independent since they simply scan the
memory operands.  They can live in TargetInstrInfoImpl.

llvm-svn: 137063

Fix encodings for Thumb ASR and LSR immediate operands.  They encode the range 1-32, with 32 encoded as 0.

llvm-svn: 137062

Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack.  PR10611.

llvm-svn: 137061

Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.

- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059

X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

llvm-svn: 137050

Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986

More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982

Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.

llvm-svn: 136978

The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969

llvm-svn: 136968

<rdar://problem/9878189>

llvm-svn: 136962

llvm-svn: 136956

llvm-svn: 136954

llvm-svn: 136942

Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940

llvm-svn: 136899

LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets.  Add an appropriate immediate type for them.

llvm-svn: 136896

the PVS-studio tool.

llvm-svn: 136878

Move the reloc size assert into AsmBackend - where it is more apropos.

llvm-svn: 136855

Fixes PR10527.

llvm-svn: 136853

Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845

llvm-svn: 136837

New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.

I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813

llvm-svn: 136803

This fixes PR10575.

llvm-svn: 136787

ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering.  Not especially pretty, but seems to work well enough.  If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha.

llvm-svn: 136737

The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.

llvm-svn: 136711

Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.

llvm-svn: 136707

llvm-svn: 136705

Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704

  shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

llvm-svn: 136691

llvm-svn: 136690

to compile a working hello world on FreeBSD/PPC32.

llvm-svn: 136689

Krasin!

llvm-svn: 136663