llvm-svn: 183907

Now that the PRED_BAD has been removed, this is failing the Clang
-Werror build due to -Wcovered-switch-default.

llvm-svn: 183863

I'm taking David Blaikie's suggestion to use an
Optional<PPC::Predicate> return value instead.  That's the right
solution for this problem.  Thanks for pointing out that possibility!

llvm-svn: 183858

Introducing PRED_BAD caused some unexpected warnings that are now
suppressed.

llvm-svn: 183854

This is a preparatory patch for fast-isel support.  The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined.  These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp.  This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.

No functional change intended.

llvm-svn: 183844

Allows returning a PPC::Predicate from a function with a no-predicate
value possible.  Preparatory patch for fast-isel on PPC64 ELF.  No
behavioral change intended.

llvm-svn: 183841

[MC/DWARF] Support .debug_frame / .debug_line code alignment factors

I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.

In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4.  However, current MC code hard-codes a code
alignment factor of 1.

This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.

This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc.  Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available.  However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it.  If it turns out to be needed again at a later time, it
could be re-added with an updated interface.

llvm-svn: 183834

LLVMX86CompilationCallback2, called from inline asm.

llvm-svn: 183824

match the comments and what the instruction actually does. Noticed
on inspection.

llvm-svn: 183809

llvm-svn: 183808

llvm-svn: 183804

The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 

llvm-svn: 183802

Sign- and zero-extension folding was slightly incorrect because it wasn't checking that the shift on extensions was zero. Further, I recently added AND rd, rn, #255 as a form of 8-bit zero extension, and failed to add the folding code for it.

This patch fixes both issues.

This patch fixes both, and the test should remain the same:
  test/CodeGen/ARM/fast-isel-fold.ll

llvm-svn: 183794

No functionality changes.

llvm-svn: 183767

llvm-svn: 183744

FIXME: Introduce yet another checker but assert(0).
llvm-svn: 183736

Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value.
Behavior already present for Thumb2.

llvm-svn: 183734

This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.

llvm-svn: 183733

llvm-svn: 183731

The decoded MCInst wasn't reencoded as the same instruction

llvm-svn: 183729

  - Don't use assert(0), or tests may pass or fail according to assertions.
  - For now, The tests are marked as XFAIL for win32 hosts.

FIXME: Could we avoid XFAIL to specify triple in the RUN lines?
llvm-svn: 183728

FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk.

llvm-svn: 183727

llvm-svn: 183726

Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some
only support Thumb mode (M-class ones currently). This makes sure such CPUs
default to the correct mode and makes the AsmParser diagnose an attempt to
switch modes incorrectly.

rdar://14024354

llvm-svn: 183710

Previously LEA64_32r went through virtually the entire backend thinking it was
using 32-bit registers until its blissful illusions were cruelly snatched away
by MCInstLower and 64-bit equivalents were substituted at the last minute.

This patch makes it behave normally, and take 64-bit registers as sources all
the way through. Previous uses (for 32-bit arithmetic) are accommodated via
SUBREG_TO_REG instructions which make the types and classes agree properly.

llvm-svn: 183693

[PowerPC] Support extended sc mnemonic

A plain "sc" without argument is supposed to be treated like "sc 0"
by the assembler.  This patch adds a corresponding alias.

Problem reported by Joerg Sonnenberger.

llvm-svn: 183687

[PowerPC] Support branch mnemonics with implied CR0

The extended branch mnemonics are supposed to use an implied CR0
if there is no explicit condition register specified.  This patch
adds extra variants of the mnemonics to this effect.

Problem reported by Joerg Sonnenberger.

llvm-svn: 183686

[PowerPC] Use multiclass to generate extended branch mnemonics

This patch removes some redundancy by generating the extended branch
mnemonics via a multiclass.

No change in behaviour expected.

llvm-svn: 183685

llvm-svn: 183682

llvm-svn: 183657

ISB should only accepts full system sync, other options are reserved

llvm-svn: 183656

[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space

llvm-svn: 183652

the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.

llvm-svn: 183633

Changes to ARM unwind opcode assembler:

* Fix multiple .save or .vsave directives.  Besides, the
  order is preserved now.

* For the directives which will generate multiple opcodes,
  such as ".save {r0-r11}", the order of the unwind opcode
  is fixed now, i.e. the registers with less encoding value
  are popped first.

* Fix the $sp offset calculation.  Now, we can use the
  .setfp, .pad, .save, and .vsave directives at any order.

Changes to test cases:

* Add test cases to check the order of multiple opcodes
  for the .save directive.

* Fix the incorrect $sp offset in the test case.  The
  stack pointer offset specified in the test case was
  incorrect.  (Changed test cases: ehabi-mc-section.ll and
  ehabi-mc.ll)

* The opcode to restore $sp are slightly reordered.  The
  behavior are not changed, and the new output is same
  as the output of GNU as.  (Changed test cases:
  eh-directive-pad.s and eh-directive-setfp.s)

llvm-svn: 183627

llvm-svn: 183626

The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register.

These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets.

llvm-svn: 183624

llvm-svn: 183613

Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF

llvm-svn: 183612

llvm-svn: 183611

Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

llvm-svn: 183610