These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.

Fix PR6489.

llvm-svn: 97742

clobber registers in a different order.

llvm-svn: 97741

llvm-svn: 97740

register if it isn't possible to match the indexes *and* the base.
This fixes some fast isel rejects of load instructions on oggenc.

llvm-svn: 97739

Instruction (PLI) for disassembly only.

According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"].  The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.

llvm-svn: 97731

llvm-svn: 97709

llvm-svn: 97691

MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675

Fix PR6444, note still doesn't compile libgcc2 all the way, but fixes that error.  May not fix it in an ABI complient way.  It wasn't clear what gcc does

llvm-svn: 97660

and STRHT for disassembly only.

llvm-svn: 97655

better done by dag combine.

llvm-svn: 97633

for disassembly only.

llvm-svn: 97632

'dsload' pattern.  tblgen doesn't check patterns to see if they're
textually identical.  This allows better factoring.

llvm-svn: 97630

that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629

- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628

llvm-svn: 97617

disassembly only.

llvm-svn: 97614

llvm-svn: 97606

We still preprocess calls and fp return stuff.

llvm-svn: 97598

now that isel handles chains more aggressively.  This also
allows us to make isLegalToFold non-virtual.

llvm-svn: 97597

CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)

llvm-svn: 97596

llvm-svn: 97595

the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.

llvm-svn: 97582

SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.

llvm-svn: 97573

Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.

Ref: A8.3 Conditional execution
llvm-svn: 97571

llvm-svn: 97567

llvm-svn: 97565

llvm-svn: 97564

DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555

Fixes PR5309.

llvm-svn: 97554

llvm-svn: 97536

respectively.

llvm-svn: 97531

now that it is gone.

llvm-svn: 97516

Remove the optimize for code size limitation on r67917. Optimize 64-bit imul by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization.

llvm-svn: 97507

problems.  rdar://7697850.

llvm-svn: 97500

llvm-svn: 97485

bit should be set to 0 instead of 1.

llvm-svn: 97481

llvm-svn: 97460

llvm-svn: 97450

llvm-svn: 97443