llvm-svn: 37126

llvm-svn: 37125

llvm-svn: 37124

llvm-svn: 37123

llvm-svn: 37121

llvm-svn: 37120

llvm-svn: 37119

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118

llvm-svn: 37117

not being generated correctly because the shl operator does not mutate its
object but returns a new value. Also, make the distinction between radix
16 and the others more clear.

llvm-svn: 37111

llvm-svn: 37105

runtime.

llvm-svn: 37104

llvm-svn: 37103

This fixes PR1423

llvm-svn: 37102

llvm-svn: 37100

llvm-svn: 37098

llvm-svn: 37097

on. This helps to speed up the debugging time by showing computational
results as the program executes.

llvm-svn: 37095

llvm-svn: 37094

llvm-svn: 37093

llvm-svn: 37092

llvm-svn: 37089

llvm-svn: 37086

llvm-svn: 37084

llvm-svn: 37081

llvm-svn: 37080

llvm-svn: 37071

test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll

llvm-svn: 37069

llvm-svn: 37067

llvm-svn: 37066

llvm-svn: 37065

llvm-svn: 37064

llvm-svn: 37057

linkage or hidden visibility.

llvm-svn: 37055

CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054

llvm-svn: 37052

v1 =
r2 = move v1
   = op r2<kill>
...
r2 = move v1
   = op r2<kill>

Clear the first r2 kill if v1 and r2 are joined.

llvm-svn: 37050

When marking a register as being implicitly defined, make sure to clear its partial use info as well.

llvm-svn: 37046

and used in the same module.

llvm-svn: 37044

llvm-svn: 37042