llvm-svn: 80892

X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.

No functionality changes.

llvm-svn: 80880

conditional moves as a subtarget feature.  This is the easy part of 
PR4841.

llvm-svn: 80763

instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.

llvm-svn: 78746

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

llvm-svn: 75276

llvm-svn: 75275

add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.

llvm-svn: 75273

elimiantes the last use of GVRequiresExtraLoad, so delete it.

llvm-svn: 75244

need for other purposes.

llvm-svn: 75243

is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.

llvm-svn: 75237

llvm-svn: 75232

more complex and slow than just directly testing what we care about.

llvm-svn: 75231

split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.

llvm-svn: 75230

llvm-svn: 75229

code which conflated RIPRel PIC with x86-64.  Fix these to just check for X86-64
directly.

llvm-svn: 75092

Fix a subtarget feature bug.

llvm-svn: 74428

Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.

llvm-svn: 74350

llvm-svn: 73836

- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10

New processor names match those used by gcc.

Patch by Paul Redmond!

llvm-svn: 72434

llvm-svn: 72335

llvm-svn: 72160

llvm-svn: 61715

Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.

llvm-svn: 61557

especially in the case of addresses computed from loop induction
variables.

llvm-svn: 61075

llvm-svn: 60609

being both a namespace and a variable name.

llvm-svn: 60208

llvm-svn: 56888

`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.

llvm-svn: 56885

llvm-svn: 50649

the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634

llvm-svn: 49158

llvm-svn: 49129

llvm-svn: 49048

llvm-svn: 48691

llvm-svn: 47002

Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax

llvm-svn: 46850

llvm-svn: 46681

llvm-svn: 45494

llvm-svn: 45418