llvm-svn: 41013

llvm-svn: 41012

Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).

llvm-svn: 41010

llvm-svn: 41009

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.

llvm-svn: 41005

llvm-svn: 41001

llvm-svn: 40998

llvm-svn: 40997

llvm-svn: 40991

llvm-svn: 40990

llvm-svn: 40989

"| grep foo | wc -l | grep 2" idiom used by many tests, so that, for
example, tests don't mistakenly accept a count of 12 when 2 is
expected. Also, the new form is more consice: "| grep foo | count 2".

llvm-svn: 40988

use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.

llvm-svn: 40987

llvm-svn: 40986

llvm-svn: 40985

memcpy with zero length is hugely expensive, so avoid it.  This speeds up coallescing from 1.17s to 0.88s on siod.

llvm-svn: 40984

an empty vector.  This speeds up llc slightly.

llvm-svn: 40983

llvm-svn: 40982

llvm-svn: 40981

llvm-svn: 40980

llvm-svn: 40979

llvm-svn: 40978

not split condition constraints.

llvm-svn: 40977

llvm-svn: 40976

llvm-svn: 40975

to handle values bigger than double.  If we assume host==target and host
long double works correctly, this is not too bad, but we don't want to
have that limitation longterm.  I could implement accepting double
constants as long double or something like that, which would lead to
incorrect codegen with no errors; the more I think about that the worse
it seems.  Rather than do such a hack that would be backed out later,
I'm settling for giving reasonable error messages, for now.

llvm-svn: 40974

llvm-svn: 40973

divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead.

llvm-svn: 40972

alloca, increase the alignment of the load, turning it into an aligned load.

This allows us to compile:

#include <xmmintrin.h>
__m128i foo(__m128i x){
 static const unsigned int c_0[4] = { 0, 0, 0, 0 };
	  __m128i v_Zero = _mm_loadu_si128((__m128i*)c_0);
  x  = _mm_unpacklo_epi8(x,  v_Zero);
  return x;
}

into:

_foo:
	punpcklbw	_c_0.5944, %xmm0
	ret
	.data
	.lcomm	_c_0.5944,16,4		# c_0.5944

instead of:

_foo:
	movdqu	_c_0.5944, %xmm1
	punpcklbw	%xmm1, %xmm0
	ret
	.data
	.lcomm	_c_0.5944,16,2		# c_0.5944

llvm-svn: 40971

GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.

llvm-svn: 40970

llvm-svn: 40965

llvm-svn: 40961

llvm-svn: 40960

(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958

llvm-svn: 40957

to do so.

llvm-svn: 40955

llvm-svn: 40953

llvm-svn: 40952

llvm-svn: 40950