to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.

llvm-svn: 96384

llvm-svn: 96383

They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.

This patch handles ARM mode. Thumb2 will follow.

llvm-svn: 96381

o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)

llvm-svn: 96380

branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.

llvm-svn: 96360

We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.

llvm-svn: 96297

as suggested by Bob Wilson.

llvm-svn: 96153

llvm-svn: 96075

llvm-svn: 96063

Plus add two formats: MiscFrm and ThumbMiscFrm.  Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.

llvm-svn: 96032

llvm-svn: 96019

llvm-svn: 96010

llvm-svn: 95999

MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955

llvm-svn: 95916

llvm-svn: 95884

as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873

llvm-svn: 95784

llvm-svn: 95603

Rn operand.

llvm-svn: 95025

llvm-svn: 94955

cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119

Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.

llvm-svn: 93829

"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758

clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564

llvm-svn: 91555

between BR_JTr and STREXD.

llvm-svn: 91339

llvm-svn: 91333

llvm-svn: 91329

llvm-svn: 91327

llvm-svn: 91313

llvm-svn: 91307

llvm-svn: 91305

llvm-svn: 91284

just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200

memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.

llvm-svn: 91150

llvm-svn: 91140

llvm-svn: 91090

llvm-svn: 91053

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003