PLI requires both the Thumb2 and the ARMv7 feature.

Related to <rdar://problem/14403733>.

llvm-svn: 186620

https://bugs.freedesktop.org/show_bug.cgi?id=66175

llvm-svn: 186616

llvm-svn: 186615

llvm-svn: 186614

llvm-svn: 186613

llvm-svn: 186576

llvm-svn: 186574

This should be the last of the R.SBG patches for now.

llvm-svn: 186573

Also, fix the namespace for two instructions that I missed previously.

llvm-svn: 186572

The original code only folded SRA into ROTATE ... SELECTED BITS
if there was no outer shift.  This patch splits out that check
and generalises it slightly.  The extra cases aren't really that
interesting, but this is paving the way for RNSBG support.

llvm-svn: 186571

Extend the previous R.SBG patches to handle XORs.

llvm-svn: 186570

In hindsight, using "RISBG" for something that can be any type of
R.SBG instruction was a bit confusing, so this renames it to RxSBG.
That might not be the best choice either, since there is an instruction
called RXSBG, but hopefully the lower-case letter stands out enough.

While there I fixed a couple of GNUisms that had crept in --
sorry about that!

llvm-svn: 186569

The N3VDIntnp pattern takes bits<5> and I gave it 6 bits.

Thanks to Jiangning Liu for spotting it!

llvm-svn: 186568

This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.

llvm-svn: 186567

llvm-svn: 186566

Support for dynamic stack alignments in the PPC backend has been unfinished, in
part because it depends on dynamic stack realignment (which I only just
recently implemented fully). Now we can also support dynamic allocas with
higher than the default target stack alignment (16 bytes).

In order to round-up the requested size to the maximum requested alignment, we
need an additional register to hold the rounded-up size. We're already using one
scavenged register to hold the previous stack-pointer value (which needs to be
stored with the signal-safe stdux update), and so when we have dynamic allocas
and a large alignment, we allocate two emergency spill slots for the scavenger.

llvm-svn: 186562

First, this changes the base-pointer implementation to remove an unnecessary
complication (and one that is incompatible with how builtin SjLj is
implemented): instead of using r31 as the base pointer when it is not needed as
a frame pointer, now the base pointer will always be r30 when needed.

Second, we introduce another pseudo register, BP, which is used just like the FP
pseudo register to refer to the base register before we know for certain what
register it will be.

Third, we now save BP into the jmp_buf, and restore r30 from that slot in
longjmp.  If the function that called setjmp did not use a base pointer, then
r30 will be overwritten by the setjmp-calling-function's restore code. FP
restoration (which is restored into r31) works the same way.

llvm-svn: 186545

llvm-svn: 186529

llvm-svn: 186528

This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions.

llvm-svn: 186512

llvm-svn: 186507

This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.

llvm-svn: 186504

Patch by Robert Lytton.

llvm-svn: 186500

llvm-svn: 186496

Make x86 fast-isel correctly choose between aligned and unaligned operations for vector stores. Fixes PR16640.

llvm-svn: 186491

My patch 'r183551 - ARM FastISel integer sext/zext improvements' was incorrect when emitting ARM register-immediate ASR, LSL, LSR instructions: they are pseudo-instructions in ARMInstrInfo.td and I should have used MOVsi instead.

This is not an issue when code is generated through a .s file, but is an issue when generated straight to a .o (-filetype=obj).

llvm-svn: 186489

Because the builtin longjmp implementation uses a CTR-based indirect jump, when
the control flow arrives at the builtin setjmp call, the CTR register has
necessarily been clobbered. Correspondingly, this adds CTR to the list of
implicit definitions of the builtin setjmp pseudo instruction.

We don't need to add CTR to the implicit definitions of builtin longjmp
because, even though it does clobber the CTR register, the control flow cannot
return to inside the loop unless there is also a builtin setjmp call.

llvm-svn: 186488

This builds on some frame-lowering code that has existed since 2005 (r24224)
but was disabled in 2008 (r48188) because it needed base pointer support to
function correctly. This implementation follows the strategy suggested by Dale
Johannesen in r48188 where the following comment was added:

  This does not currently work, because the delta between old and new stack
  pointers is added to offsets that reference incoming parameters after the
  prolog is generated, and the code that does that doesn't handle a variable
  delta.  You don't want to do that anyway; a better approach is to reserve
  another register that retains to the incoming stack pointer, and reference
  parameters relative to that.

And now we do exactly that. If we don't need a frame pointer, then we use r31
as a base pointer. If we do need a frame pointer, then we use r30 as a base
pointer. The base pointer retains the value of the stack pointer before it was
decremented in the prologue. We then use the base pointer to resolve all
negative frame indicies. The basic scheme follows that for base pointers in the
X86 backend.

We use a base pointer when we need to dynamically realign the incoming stack
pointer. This currently applies only to static objects (dynamic allocas with
large alignments, and base-pointer support in SjLj lowering will come in future
commits).

llvm-svn: 186478

Move string pointer from being a static class member to just a static global in the one file its needed in.

llvm-svn: 186476

block. Blocks that have an indirect branch terminator, even if it's not the
last terminator, should still be treated as unanalyzable.

<rdar://problem/14437274>

Reducing a useful regression test case is proving difficult - I hope to have
one soon.

llvm-svn: 186461

This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]

See A8.8.129 in the ARM ARM (DDI 0406C.b).

Fixes <rdar://problem/14403733>.

llvm-svn: 186459

This centralizes the handling of O_BINARY and opens the way for hiding more
differences (like how open behaves with directories).

llvm-svn: 186447

Use PMIN/PMAX for UGE/ULE vector comparions to reduce the number of required
instructions. This trick also works for UGT/ULT, but there is no advantage in
doing so. It wouldn't reduce the number of instructions and it would actually
reduce performance.

Reviewer: Ben

radar:5972691

llvm-svn: 186432

llvm-svn: 186429

Previously an asm operand with no operand modifier would give the error
"invalid operand in inline asm".

llvm-svn: 186407

We'd forgotten to provide string representations for the special ARMISD atomic
nodes; this adds them in. No effect on CodeGen, just makes the output of
"-view-whatever-dags" slightly more readable.

llvm-svn: 186406

llvm-svn: 186405

llvm-svn: 186403

CodeGen support will come later.

llvm-svn: 186401

Another patch in the series to make more use of R.SBG.  This one extends
r186072 and r186073 to handle cases where the AND is inside the shift.

llvm-svn: 186399