Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt

llvm-svn: 75035

Also remove trailing semicolon.

llvm-svn: 75027

llvm-svn: 75020

llvm-svn: 75019

cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018

llvm-svn: 75016

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

Mark sublw_cc and subfw_cc as Terminator insns so that they are part of the terminator insns for a basic block alongwith branch insns. This way a copy is not getting inserted between cmp and branch during PHIElimination disturbing the status flags.

llvm-svn: 74992

these instructions, no autoupgrade or backwards compatibility support is
provided.

llvm-svn: 74991

Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.

llvm-svn: 74988

llvm-svn: 74976

llvm-svn: 74974

Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.

llvm-svn: 74972

U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86RegisterInfo.h

Temporarily revert. This was causing an infinite loop in the linker on Leopard.

llvm-svn: 74970

patch, instead of one I didn't.

llvm-svn: 74968

prologue like this:

__Z3fooi:
Leh_func_begin1:
LBB1_0: ## entry
        pushl   %ebp
Llabel1:
        movl    %esp, %ebp
Llabel2:
        pushl   %esi
Llabel3:
        subl    $20, %esp
        call    "L1$pb"
"L1$pb":
        popl    %esi

The "pushl %ebp" needs a table entry specifying the offset. The "movl %esp,
%ebp" makes %ebp the new stack frame register, so that needs to be specified in
DWARF. And "pushl %esi" saves the callee-saved %esi register, which also needs
to be specified in DWARF.

Before, all of this logic was in one method. This didn't work too well, because
as you can see there are multiple FDE line entries that need to be created.

This fix creates the "MachineMove" objects directly when they're needed; instead
of waiting until the end, and losing information.

llvm-svn: 74952

llvm-svn: 74946

llvm-svn: 74938

llvm-svn: 74931

llvm-svn: 74895

llvm-svn: 74889

llvm-svn: 74888

in PIC modes (in accordance with existing comment).
gcc.apple/asm-block-25.c

llvm-svn: 74886

PIC16 developers, please verify. Thanks.

llvm-svn: 74880

llvm-svn: 74879

llvm-svn: 74871

llvm-svn: 74868

llvm-svn: 74866

pic16 doesn't have a Data64bitsDirective. Set it NULL explicitly to tell the generic code to not pick the default.

llvm-svn: 74839

llvm-svn: 74838

Implement _section macro to allow users to place objects in specific sections.
Implement _address macro to allow users to place objects at a particular address.
Placing objects at a memory address:
crate a unique section name from varname, address, object type and put that section at specified address. Mark this section a full (size = banksize) so that other objects do not compete for it while placing objects to sections in AsmPrinter.

llvm-svn: 74822

llvm-svn: 74819

cleanup, removed some #includes and moved Object Code Emitter out-of-line.

llvm-svn: 74813

llvm-svn: 74779

llvm-svn: 74778

llvm-svn: 74777

llvm-svn: 74776

The change in the .td file is to mark the side effects of mov insn.

llvm-svn: 74768

Don't spill to the CR save area when using the SVR4 ABI for now.
Don't rely on constants assigned for registers to be in order (they aren't assigned in order).
Make sure CR bits are mapped to the corresponding CR field.

llvm-svn: 74767

Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.

llvm-svn: 74766