llvm-svn: 37959

llvm-svn: 37940

llvm-svn: 37932

llvm-svn: 37931

llvm-svn: 37930

llvm-svn: 37926

llvm-svn: 37923

llvm-svn: 37917

llvm-svn: 37915

llvm-svn: 37914

Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913

llvm-svn: 37911

llvm-svn: 37898

llvm-svn: 37897

llvm-svn: 37896

Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.

llvm-svn: 37895

llvm-svn: 37894

llvm-svn: 37893

- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.

llvm-svn: 37892

llvm-svn: 37891

their names are changed.

llvm-svn: 37876

llvm-svn: 37866

Still need to have JIT generate this code.

llvm-svn: 37863

llvm-svn: 37853

model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847

the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.

llvm-svn: 37844

llvm-svn: 37801

llvm-svn: 37790

llvm-svn: 37786

llvm-svn: 37784

llvm-svn: 37768

llvm-svn: 37756

llvm-svn: 37737

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719

between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718

llvm-svn: 37717

llvm-svn: 37716

llvm-svn: 37705

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704