llvm-svn: 97836

node which has a flag.  That flag in turn was used by an
already-selected adde which turned into an ADC32ri8 which
used a selected load which was chained to the load we
folded.  This flag use caused us to form a cycle.  Fix
this by not ignoring chains in IsLegalToFold even in
cases where the isel thinks it can.

llvm-svn: 97791

llvm-svn: 97789

llvm-svn: 97781

llvm-svn: 97779

rounding correctly. This implementation is a generalization of
the x86_64 code in compiler-rt.

This fixes rdar://7683708.

llvm-svn: 97778

llvm-svn: 97765

positive where pointers would be leaked on llvm_shutdown.

llvm-svn: 97759

as nounwind are marked with a -1 call-site value. This is necessary to, for
example, correctly process exceptions thrown from within an "unexpected"
execption handler (see SingleSource/Regression/C++/EH/expection_spec_test.cpp).

llvm-svn: 97757

llvm-svn: 97752

llvm-svn: 97747

llvm-svn: 97738

llvm-svn: 97735

llvm-svn: 97713

Look ahead a bit to determine if a physical register def that is not marked dead is really alive. This is necessary to catch a lot of common cse opportunities for targets like x86.

llvm-svn: 97706

as the very last thing before node emission.  This should
dramatically reduce the number of times we do 'MatchAddress'
on X86, speeding up compile time.  This also improves comments
in the tables and shrinks the table a bit, now down to 
80506 bytes for x86.

llvm-svn: 97703

a patch my Micah Villmow for PR6465.

llvm-svn: 97692

llvm-svn: 97690

Fix a logic error. An instruction that has a live physical register def cannot be CSE'ed, but it *can* be used to replace a common subexpression.

llvm-svn: 97688

llvm-svn: 97687

Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip over only virtual register defs. This matches what isEqual() is doing.

llvm-svn: 97680

Re-apply r97667 but with a little bit of thought put into the patch. This implements a special DenseMapInfo trait for DenseMap<MachineInstr*> that compare the value of the MachineInstr rather than the pointer value. Since the hashing and equality test functions ignore defs it's useful for doing CSE kind optimization.

llvm-svn: 97678

llvm-svn: 97673

llvm-svn: 97670

llvm-svn: 97667

CSE and recursive RAUW calls delete a node from the use list,
invalidating the use list iterator. There's currently no known
way to reproduce this in an unmodified LLVM, however there's no
fundamental reason why a SelectionDAG couldn't be formed which
would trigger this case.

llvm-svn: 97665

Machine CSE work in progress. It's doing some CSE now. But implicit def of physical registers are getting in the way.

llvm-svn: 97664

llvm-svn: 97663

--- Reverse-merging r97592 into '.':
U    lib/CodeGen/TargetLoweringObjectFileImpl.cpp

llvm-svn: 97657

Scope accelerator.

llvm-svn: 97652

entry we're about to process is obviously going to fail, don't
bother pushing a scope only to have it immediately be popped.
This avoids a lot of scope stack traffic in common cases.

Unfortunately, this requires duplicating some of the predicate
dispatch.  To avoid duplicating the actual logic I pulled each
predicate out to its own static function which gets used in
both places.

llvm-svn: 97651

SwitchOpcodeMatcher) and have DAGISelMatcherOpt form it.  This
speeds up selection, particularly for X86 which has lots of 
variants of instructions with only type differences.

llvm-svn: 97645

llvm-svn: 97635

llvm-svn: 97631

- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628

llvm-svn: 97627

long test(long x) { return (x & 123124) | 3; }

Currently compiles to:

_test:
        orl     $3, %edi
        movq    %rdi, %rax
        andq    $123127, %rax
        ret

This is because instruction and DAG combiners canonicalize

  (or (and x, C), D) -> (and (or, D), (C | D))

However, this is only profitable if (C & D) != 0. It gets in the way of the
3-addressification because the input bits are known to be zero.

llvm-svn: 97616

CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)

llvm-svn: 97596

Place the LSDA into the TEXT section on Mach-O. This saves space.

llvm-svn: 97592

llvm-svn: 97581