into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

consuming for a simple optimization.

llvm-svn: 95671

For disassembly only.

A8.6.300

llvm-svn: 95669

Patch by M Wahab!

llvm-svn: 95668

llvm-svn: 95650

llvm-svn: 95649

llvm-svn: 95647

llvm-svn: 95646

llvm-svn: 95643

xform.

llvm-svn: 95642

llvm-svn: 95641

	movl	$3735928559, a          ## inst: <MCInst 1273 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(a)> <MCOperand Reg:0> <MCOperand Expr:(3735928559)>>

after:

	movl	$3735928559, a          ## <MCInst #1273
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Imm:1>
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Expr:(a)>
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Expr:(3735928559)>>

llvm-svn: 95637

Previously spill registers, whose def indexes are not defined, would sometimes be improperly marked as coalescable with conflicting registers. The new findCoalesces routine conservatively assumes that any register with at least one undefined def is not coalescable with any register it interferes with.

llvm-svn: 95636

llvm-svn: 95634

Added copy sensible construction & assignment to PBQP graphs and fixed a memory access bug in the heuristic solver.

llvm-svn: 95633

Initial skeleton and SCEVUnknown lowering implemented,
the rest should come relatively quickly.  Move testcase
to new directory.

Move pass to right before SimplifyLibCalls - which is
moved down a bit so we can take advantage of a few opts.

llvm-svn: 95628

llvm-svn: 95627

llvm-svn: 95624

direct MCExpr equivalents. Don't use MCExpr::Shr because it isn't
consistent between targets.

llvm-svn: 95620

Document that MCExpr::Div, Mod, and the comparison operators are all
signed operators.

Document that the comparison operators' results are target-dependent.

Document that the behavior of shr is target-dependent.

llvm-svn: 95619

llvm-svn: 95616

llvm-svn: 95609

llvm-svn: 95603

MCSymbol, we can remove the 'suffix' argument of 
GetBlockAddressSymbol.  Do so.

llvm-svn: 95601

 2 files changed, 48 insertions(+), 83 deletions(-)

llvm-svn: 95599

backend to use X86MCTargetExpr, simplifying a bunch of code.

llvm-svn: 95595

for register tokens.  Before, if it encountered
'%al,' it would report 'al,' as the token.  Now it
correctly reports '%al'.

llvm-svn: 95594

llvm-svn: 95593

expression; don't go into an infinite loop if it does.

llvm-svn: 95591

representing @GOT and friends.  Use it for
personality references as a first use.

llvm-svn: 95588

llvm-svn: 95587

The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584

in global initializers. Instead of aborting, attempt to fold them on the
spot. If folding succeeds, emit the folded expression instead.

This fixes PR6255.

llvm-svn: 95583

llvm-svn: 95582

we can get in here if FastISel gives up in a block.
(Actually the two copies of this need to be unified.  Later.)

llvm-svn: 95579

for blocks ending in "unreachable".

llvm-svn: 95565

its current purpose.

llvm-svn: 95564

llvm-svn: 95560

llvm-svn: 95559