llvm-svn: 102594

llvm-svn: 102590

llvm-svn: 102585

llvm-svn: 102584

llvm-svn: 102581

llvm-svn: 102577

llvm-svn: 102573

- Also, update dbg_value is the value is being re-matted from a frame slot, e.g. fixed slots for arguments.

llvm-svn: 102565

llvm-svn: 102558

Operand size override prefix to be part of their records.

llvm-svn: 102556

Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.

llvm-svn: 102554

llvm-svn: 102547

llvm-svn: 102545

llvm-svn: 102544

be installed.  Disable it by default.

llvm-svn: 102531

Add sizes non-floating point versions for the eh sjlj intrinsic expansions.

rdar://7895451

llvm-svn: 102526

Update tests. Now DBG_VALUE instruction is created only if alloca corresponding to llvm.dbg.declare is missing.

llvm-svn: 102524

Patch by Lars R in PR6961.

llvm-svn: 102523

metadata references in non-function-local MDNodes should drop to 
null.

llvm-svn: 102519

Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707

llvm-svn: 102518

alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).

llvm-svn: 102515

While lowering dbg_declare, emit DBG_VALUE machine instruction if alloca matching llvm.dbg.declare intrinsic is missing.

llvm-svn: 102513

update them. Computing kill flags is notoriously difficult, and the coalescer
would get it wrong sometimes, and it would completely skip physical registers.

Now we simply remove kill flags based on the live intervals after coalescing.
This is a few percent slower, but now we get correct kill flags for physical
registers after coalescing.

llvm-svn: 102510

instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

llvm-svn: 102509

after all.

llvm-svn: 102508

llvm-svn: 102505

llvm-svn: 102504

llvm-svn: 102493

llvm-svn: 102492

llvm-svn: 102488

llvm-svn: 102487

llvm-svn: 102486

Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).

llvm-svn: 102485

ForcedAlignBits argument, tweaking the single client of it.

llvm-svn: 102484

llvm-svn: 102483

llvm-svn: 102482

llvm-svn: 102481

of dependence and define trap values in terms of dependence, instead
of trying to cover the concept with a flurry of ad-hoc rules.

The dependence model isn't complete yet, but it's already much more
rigorous than the description it replaces.

llvm-svn: 102479

llvm-svn: 102478

llvm-svn: 102477