The index stored in the RegDefIter is one after the current index.  When getting the index, decrement it so that it points to the current element.  Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.

llvm-svn: 133923

Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.

llvm-svn: 133917

Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902

The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.

llvm-svn: 133838

llvm-svn: 133821

that takes an ArrayRef.

llvm-svn: 133615

llvm-svn: 133567

1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108

llvm-svn: 133503

source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )

llvm-svn: 133424

llvm-svn: 133389

llvm-svn: 133388

instead of scalarizing, and doing an element-by-element truncat.

llvm-svn: 133382

llvm-svn: 133348

llvm-svn: 133347

range without a libcall to a new mulo<mode> libcall
that we'd have to create.

Finishes the rest of rdar://9090077 and rdar://9210061

llvm-svn: 133318

llvm-svn: 133307

calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061

llvm-svn: 133288

In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).

<rdar://problem/9624323>

llvm-svn: 133210

BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184

Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand.  This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.

llvm-svn: 133178

This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.

Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.

llvm-svn: 133170

llvm-svn: 133124

Add a new MVT::untyped.  This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers).  We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them.  Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.

llvm-svn: 133106

Added a test case for handling physreg aliases during pre-RA-sched.

llvm-svn: 133063

llvm-svn: 133057

Enable the simplification of truncating-store after fixing the usage of
GetDemandBits (which must operate on the vector element type).

Fix the a usage of getZeroExtendInReg which must also be done on scalar types.

llvm-svn: 133052

converted to add x,x if x is a undef.  add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.

llvm-svn: 133022

Add a testcase for checking the integer-promotion of many different vector
types (with power of two types such as 8,16,32 .. 512).

Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding
only if the target of the conversion is an integer (when the type action is
scalarize).

Add handling to the legalization of vector load/store in cases where the saved
vector is integer-promoted.

llvm-svn: 132985

llvm-svn: 132984

or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976

only if the number of packed elements is a power of two.
Bug found in Duncan's testcase.

llvm-svn: 132923

types such as i33 were rounded to i32. Originated from Duncan's testcase.

llvm-svn: 132893

Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors:  i8 -> <1 x i1> (from Duncan's
testcase).

llvm-svn: 132892

llvm-svn: 132872

llvm-svn: 132871

llvm-svn: 132863

Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine.  Part of rdar://9562809.

The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.

llvm-svn: 132809

No functional change.

Part of PR6965

llvm-svn: 132763

llvm-svn: 132751

I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.

llvm-svn: 132701