llvm-svn: 134633

llvm-svn: 134630

llvm-svn: 134629

llvm-svn: 134628

llvm-svn: 134627

llvm-svn: 134626

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

llvm-svn: 134622

llvm-svn: 134616

llvm-svn: 134614

multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609

llvm-svn: 134608

llvm-svn: 134606

llvm-svn: 134595

Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.

llvm-svn: 134590

llvm-svn: 134577

Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.

llvm-svn: 134569

llvm-svn: 134547

llvm-svn: 134546

This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540

Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533

llvm-svn: 134527

llvm-svn: 134525

push with a small constant produces a 2-byte push.

llvm-svn: 134501

llvm-svn: 134457

Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.

llvm-svn: 134424

If the function allocates reserved stack space for callee argument frames,
estimateStackSize() needs to account for that, as it doesn't show up as
ordinary frame objects. Otherwise, a callee with a large argument list will
throw off the calculations for whether to allocate an emergency spill slot
and we get assert() failures in the register scavenger.

rdar://9715469

llvm-svn: 134415

Noticed by Benjamin Kramer!

llvm-svn: 134376

This is what both the ABI and clang says.

llvm-svn: 134367

llvm-svn: 134323

llvm-svn: 134311

Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

llvm-svn: 134307

up the valid constant check earlier.

rdar://9692967

llvm-svn: 134286

llvm-svn: 134281

llvm-svn: 134279

llvm-svn: 134264

The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992

llvm-svn: 134261

llvm-svn: 134259

  itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257

(low two bits always zero, so off by one bit of encoded value).

llvm-svn: 134247