llvm-svn: 145893

rdar://10528060

llvm-svn: 145891

Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890

This was actually a bit of a mess. TLI.setPrefLoopAlignment was clearly
documented as taking log2(bytes) units, but the x86 target would still
set a preferred loop alignment of '16'.

CodePlacementOpt passed this number on to the basic block, and
AsmPrinter interpreted it as bytes.

Now both MachineFunction and MachineBasicBlock use logarithmic
alignments.

Obviously, MachineConstantPool still measures alignments in bytes, so we
can emulate the thrill of using as.

llvm-svn: 145889

value over that much.

llvm-svn: 145888

rdar://10069056

llvm-svn: 145885

llvm-svn: 145883

Whether a fixup needs relaxation for the associated instruction is a
target-specific function, as the FIXME indicated. Create a hook for that
and use it.

llvm-svn: 145881

llvm-svn: 145880

don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684

llvm-svn: 145879

llvm-svn: 145878

per http://llvm.org/docs/CodingStandards.html#ll_naming

llvm-svn: 145873

Not right yet, as the rules for when to relax in the MCAssembler aren't
(yet) correct for ARM. This is a step in the proper direction, though.

llvm-svn: 145871

memory fences) in statistics registration, which works the same way that
ManagedStatic registration does.

llvm-svn: 145869

llvm-svn: 145866

where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150

llvm-svn: 145865

llvm-svn: 145863

rdar://10529664

llvm-svn: 145860

PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853

them.

llvm-svn: 145852

rdar://10529348

llvm-svn: 145851

O32 with relocation-model=pic too.

llvm-svn: 145850

Finish up rdar://10522016.

llvm-svn: 145846

llvm-svn: 145844

llvm-svn: 145843

Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

llvm-svn: 145842

llvm-svn: 145819

llvm-svn: 145818

llvm-svn: 145816

- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.

llvm-svn: 145810

llvm-svn: 145804

llvm-svn: 145803

Add support for vectors of pointers.

llvm-svn: 145801

not get there any other way.

llvm-svn: 145789

llvm-svn: 145783

Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781

AnalyzeBranch doesn't change the successor, just the order.

llvm-svn: 145779

-3% on ARMDissasembler.cpp.

llvm-svn: 145773

llvm-svn: 145771

Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps.

-15% on ARMDisassembler.cpp (Release build).  It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.

llvm-svn: 145770