The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed
immediate.

llvm-svn: 197506

Trying to fix buildbots after r197503 (test passes locally).

<rdar://problem/15627766>

llvm-svn: 197505

This reverts commit r197481, recommiting r197469 with an extra fix.

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which changed the initial scheduler
to source-order as part of enabling the MI Scheduler for X86.

This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to
try to save %flags, and adds a test that catches the bad behavior of
r197469.

<rdar://problem/15627766>

llvm-svn: 197503

This will be tested from clang.

llvm-svn: 197501

These will later be used as tests for the dumper part of http://llvm-reviews.chandlerc.com/D2232

llvm-svn: 197499

llvm-svn: 197498

http://llvm.org/bugs/show_bug.cgi?id=18045

Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:

$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
      0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
      [ID=58]
  0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
    0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
  0x41dcb10: i32 = undef [ID=2]

The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.

The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal. 

P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!

llvm-svn: 197492

when using structured exception handling (SEH) on Windows 64.

http://llvm-reviews.chandlerc.com/D2378

Patch by Jonathan Liu!

llvm-svn: 197483

Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.

llvm-svn: 197482

This reverts commit r197469.

The sanitizer and dragonegg buildbots are failing, I think because of
this change.  Reverting until I figure out why.

llvm-svn: 197481

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which turned on the MI Scheduler
for X86.

<rdar://problem/15627766>

llvm-svn: 197469

With llvm-config.exe --bindir --libdir --build-mode, on Visual Studio 2010,

In build tree:
  (OBJ_ROOT)/bin/MinSizeRel
  (OBJ_ROOT)/lib/MinSizeRel
  MinSizeRel

In installed tree:
  (INSTALL_PREFIX)/bin
  (INSTALL_PREFIX)/lib
  MinSizeRel

This is enhancements since r196283.

llvm-svn: 197467

llvm-svn: 197466

Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies.

Without this, MachineCSE is powerless to handle redundant operations with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It isn't clear what combinations of subregisters can legally be tied, but the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

Test case: cse-add-with-overflow.ll.

This exposed an existing bug in
PPCInstrInfo::commuteInstruction. Thanks to Rafael for the test case:
PowerPC/crash.ll.

llvm-svn: 197465

llvm-svn: 197464

llvm-svn: 197462

Re-reading the comment I updated in previous commit, it's better to make
it more explicit and avoid ambiguity more effectively.

llvm-svn: 197458

llvm-svn: 197457

Make debugging ISel a bit easier by printing out a dump of the generated
code at the end.

llvm-svn: 197456

llvm-svn: 197451

A phi node operand or an instruction operand could be a constant expression that
can trap (division). Check that we don't vectorize such cases.

PR16729
radar://15653590

llvm-svn: 197449

DiagnosticPrinter.cpp.
These was creating a link time dependencies of IR on CodeGen and Analysis.

Part of <rdar://problem/15515174>

llvm-svn: 197447

I was testing a stale bin/llvm-lit, which now lives at bin/llvm-lit.py
on Windows.

llvm-svn: 197446

This missing parameter was causing bin/llvm-lit to run the unittests
from my primary build directory instead of my self-hosting build
directory because llvm-config was on my PATH.

This more closely matches what 'make check' will pass to lit.py.

llvm-svn: 197444

llvm-svn: 197439

The patch adds a new LLVMContext::diagnose that can be used to communicate to
the front-end, if any, that something of interest happened.
The diagnostics are supported by a new abstraction, the DiagnosticInfo class.
The base class contains the following information:
- The kind of the report: What this is about.
- The severity of the report: How bad this is.

This patch also adds 2 classes:
- DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic
will be used to switch to the new diagnostic API for LLVMContext::emitError.
- DiagnosticStackSize: For stack size reporting. Comes as a replacement of the
hard coded warning in PEI.

This patch also features dynamic diagnostic identifiers. In other words plugins
can use this infrastructure for their own diagnostics (for more details, see
getNextAvailablePluginDiagnosticKind).

This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in
the LLVMContext that should be set by the front-end to be able to map these
diagnostics in its own system.

http://llvm-reviews.chandlerc.com/D2376
<rdar://problem/15515174>

llvm-svn: 197438

Enable double to float shrinking optimizations for binary functions like 'fmin/fmax'. Fix radar:15283121

llvm-svn: 197434

Outputs branch information for unconditional branches in addition to
conditional branches. -b option must be enabled.

Also updated tests.

llvm-svn: 197432

This allows the WebKit_JS calling convention to perform partial writes on a 4
byte granularity to stack slots.

llvm-svn: 197431

llvm-svn: 197426

SI_KIL -> SI_KILL

llvm-svn: 197425

Revert "Allow MachineCSE to coalesce trivial subregister copies the same way that it coalesces normal copies."

This reverts commit r197414.

It broke the ppc64 bootstrap. I will post a testcase in a sec.

llvm-svn: 197424

llvm-svn: 197418

Pass the first integer argument (callee) in register to optimize inline caches.

llvm-svn: 197416

that it coalesces normal copies.

Without this, MachineCSE is powerless to handle redundant operations
with truncated source operands.

This required fixing the 2-addr pass to handle tied subregisters. It
isn't clear what combinations of subregisters can legally be tied, but
the simple case of truncated source operands is now safely handled:

     %vreg11<def> = COPY %vreg1:sub_32bit; GR32:%vreg11 GR64:%vreg1
     %vreg12<def> = COPY %vreg2:sub_32bit; GR32:%vreg12 GR64:%vreg2
     %vreg13<def,tied1> = ADD32rr %vreg11<tied0>, %vreg12<kill>, %EFLAGS<imp-def>

llvm-svn: 197414

llvm-svn: 197413

Produce them in the same order on every target. The order is that of
getStringRepresentation: e|E-i*-f*-v*-a*-s*-n*-S*.

llvm-svn: 197411

While there, simplify "p3:32:32:32" to "p3:32:32".

llvm-svn: 197407

llvm-svn: 197405

llvm-svn: 197402