llvm-svn: 179875

This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873

operand type to uimm16.

Patch by Vladimir Medic.

llvm-svn: 179872

indended.
Part of rdar://13663589

llvm-svn: 179871

qualifiers don't necessarily begin with an identifier (e.g., ::foo::bar).

llvm-svn: 179867

llvm-svn: 179866

llvm-svn: 179865

llvm-svn: 179856

Patch from Mihail Popa

llvm-svn: 179854

llvm-svn: 179847

llvm-svn: 179833

llvm-svn: 179830

InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829

llvm-svn: 179820

AT&T dialect.  Test case for r179804 as well.
rdar://13674398 and PR13340.

llvm-svn: 179813

llvm-svn: 179808

This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do
I'm disabling this for now.

llvm-svn: 179807

variant/dialect.  Addresses a FIXME in the emitMnemonicAliases function.
Use and test case to come shortly.
rdar://13688439 and part of PR13340.

llvm-svn: 179804

Many PPC instructions have a so-called 'record form' which stores to a specific
condition register the result of comparing the result of the instruction with
zero (always as a signed comparison). For integer operations on PPC64, this is
always a 64-bit comparison.

This implementation is derived from the implementation in the ARM backend;
there are some differences because PPC condition registers are allocatable
virtual registers (although the record forms always use a specific one), and we
look for a matching subtraction instruction after the compare (but before the
first use) in addition to before it.

llvm-svn: 179802

This pattern started popping up in vectorized min/max reductions.

llvm-svn: 179797

In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and
handled by the DAG-based ISel.  However, X86FastISel::X86SelectLoad() makes
no such requirement.  There doesn't appear to be an x86 architectural
correctness issue with allowing potentially unaligned store instructions.
This patch removes this restriction.

Patch by Jim Stichnot.

llvm-svn: 179774

llvm-svn: 179765

llvm-svn: 179764

llvm-svn: 179751

llvm-svn: 179741

llvm-svn: 179739

This patch should not have any functional changes. 

llvm-svn: 179737

Differential Revision: http://llvm-reviews.chandlerc.com/D598

llvm-svn: 179725

llvm-svn: 179724

unable to handle cases such as __asm mov eax, 8*-8.

This patch also attempts to simplify the state machine.  Further, the error
reporting has been improved.  Test cases included, but more will be added to
the clang side shortly.
rdar://13668445

llvm-svn: 179719

for the sdiv/srem/udiv/urem bitcode instructions.  This is done for the i8,
i16, and i32 types, as well as i64 for the x86_64 target.

Patch by Jim Stichnoth

llvm-svn: 179715

getSimpleVT can only handle simple value types.

radar://13676022

llvm-svn: 179714

The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)

Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.

Patch by Mihail Popa <Mihail.Popa@arm.com>

llvm-svn: 179707

PowerPC: Mark some more patterns as isCodeGenOnly.

A couple of recently introduced conditional branch patterns
also need to be marked as isCodeGenOnly since they cannot
be handled by the asm parser.

No change in generated code.

llvm-svn: 179690

llvm-svn: 179686

llvm-svn: 179685

llvm-svn: 179684

Broken in r179657.

llvm-svn: 179669

This patch allows the Mips assembler to parse and emit nested 
expressions as instruction operands. It also extends the 
expansion of memory instructions when an offset is given as 
an expression. 

Contributer: Vladimir Medic
llvm-svn: 179657

cases to be submitted on clang side shortly.
rdar://13663768 and PR15760

llvm-svn: 179655