UnitTests for building all the unit tests.

llvm-svn: 117545

llvm-svn: 117544

llvm-svn: 117543

llvm-svn: 117538

llvm-svn: 117531

I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530

test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466]

llvm-svn: 117529

Thanks to Yuri Gribov and Vladimir Kirillov!
*BSD(s) have environ(7) in CRT startup and cannot resolve "environ" at linking llvm.so.
environ(7) is used inlib/System/Unix/Program.inc.

llvm-svn: 117528

doesn't mean that you can't get a .o file.  Apparently
this is confusing :)

llvm-svn: 117523

llvm-svn: 117520

- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519

by the number of defs first for it to match the instruction itinerary.

llvm-svn: 117518

Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514

llvm-svn: 117513

llvm-svn: 117512

llvm-svn: 117511

llvm-svn: 117510

complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509

Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins.

llvm-svn: 117506

the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505

llvm-svn: 117502

for specifying fractional bits for fixed point conversions.

llvm-svn: 117501

llvm-svn: 117496

llvm-svn: 117495

llvm-svn: 117494

llvm-svn: 117485

llvm-svn: 117483

elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482

llvm-svn: 117481

llvm-svn: 117478

llvm-svn: 117477

llvm-svn: 117475

llvm-svn: 117474

There are currently 100 references to COFF::IMAGE_SCN in 6 files
and 11 different functions. Section to attribute mapping really
needs to happen in one place to avoid problems like this.

llvm-svn: 117473

llvm-svn: 117472

llvm-svn: 117471

llvm-svn: 117469

llvm-svn: 117468

llvm-svn: 117466

llvm-svn: 117463